Design Rule Checks

Setup and hold checks tell you whether the logic is fast enough and not too fast. There is a second family of checks that has nothing to do with the clock: design rule checks. They make sure that every pin works inside the range for which the library and the technology are valid. This article explains the three main rules, the maximum transition, the maximum capacitance and the maximum fanout, shows where the limits come from, and runs a check in the lab.

Think of the speed limit on a road. You can arrive on time and still have driven too fast, which is unsafe. Design rule checks are the speed limits of a chip: a signal can meet setup and hold and still break a limit on slew, load or fanout.

7 min read | Intermediate

What You'll Learn

• Name the main design rule checks and say what each one limits
• Explain where the limits come from: the library and the SDC file
• Read a design rule report and its slack
• Say why a design can meet timing and still violate a rule

Why Design Rules Exist

The library tables of a cell cover a limited range of input slews and loads. Inside the range the numbers are accurate because they come from simulation. Far outside the range, the tool has to extrapolate, which is a guess. Very slow edges and very heavy loads also cause real problems in a chip: a slow edge makes a gate draw more current while it switches, it makes the circuit sensitive to noise, and a heavily loaded output ages faster.

For these reasons, designers add upper limits that no pin may exceed, whatever the timing slack is. A violation of such a limit is called a design rule violation, and the checks are part of static timing analysis.

The Three Main Rules

• Maximum transition limits the slew at a pin. The slew is the time an edge takes, so a limit of 0.05 ns means no edge on that pin may be slower than 0.05 ns.
• Maximum capacitance limits the load that an output pin may drive. A cell that drives more than its limit would be too slow, and it may be unreliable.
• Maximum fanout limits how many input pins a net may drive.

There are also minimum versions of these limits, but the maximum ones are the common ones. Of the three, the transition and the capacitance limits are the ones that timing analysis is used for most. The fanout limit is often applied by the synthesis and implementation tools instead.

Where the Limits Come From

There are two sources:

• The library. Every output pin of a cell has a max_capacitance, the largest load that the cell was characterized for. The library can also have a default max_transition. The limits depend on the size of the cell, because a large cell can drive a heavy load.
• The SDC file. The commands set_max_transition, set_max_capacitance and set_max_fanout add limits for a design, a port or a block. The designer uses them to be stricter than the library, for example when a chip needs a clean clock.

set_max_transition 0.05 [current_design]
set_max_capacitance 0.01 [get_ports z]
set_max_fanout 10 [current_design]

Reading the Report

The command report_check_types prints the checks that you select. The option -violators shows only the pins that fail. Here is the maximum transition check of the demo circuit with a limit of 0.05 ns:

set_max_transition 0.05 [current_design]
report_check_types -max_slew -violators -digits 4

max slew

Pin                                      Limit      Slew     Slack
------------------------------------------------------------------
_4_/X                                   0.0500    0.0928   -0.0428 (VIOLATED)
_6_/D                                   0.0500    0.0928   -0.0428 (VIOLATED)
_3_/A                                   0.0500    0.0716   -0.0216 (VIOLATED)
_4_/A                                   0.0500    0.0716   -0.0216 (VIOLATED)
_7_/Q                                   0.0500    0.0716   -0.0216 (VIOLATED)

Each line is one pin with its limit and its actual value. The slack is the limit minus the actual value, so a negative slack is a violation. The worst pin is the output of the XOR gate _4_ and the data input _6_/D that it drives. They are the same net, so they have the same slew of 0.0928 ns, 0.0428 ns over the limit. The unit of the slack here is not the time of a path: it is the unit of the rule, ns for the transition and pF for the capacitance.

The maximum capacitance check has the same layout. For the same output _4_/X, the library limit is 0.0769 pF and the load is 0.0017 pF, so the check is met with a slack of 0.0752 pF. The output is far from its limit.

Timing Is Met but the Rule Is Violated

In the example above, the setup slack of the design is positive, 1.03 ns at the worst, and the check still has five violations. The two kinds of checks are independent. A path can be fast and still contain a pin with a slow edge, because the clock period is long and leaves a lot of room. Design rules are therefore checked in addition to setup and hold, and a design is not clean until both are clean.

The usual ways to remove a violation are to use a cell with a stronger output, to add a buffer, to split a heavy load, or to shorten a long wire. Each of them changes the timing as well, so after a fix the timing has to be checked again.

Common Mistakes

set_max_transition 0.05 [current_design]
report_check_types -max_slew -violators -digits 4