Normally STA works out the time that a path has from the clock edges. Sometimes you want to state the time directly: this path must be faster than 0.5 ns, whatever the clock does. The commands set_max_delay and set_min_delay do this. They are used for paths without a useful clock relationship, such as a combinational path through the chip, and for paths where the designer knows the requirement in nanoseconds. This article explains how they replace the clock edge in the check, and what stays the same.

7 min read | Intermediate

What You'll Learn

  • Write set_max_delay and set_min_delay for a path
  • Calculate the required time and the slack of a path with a max delay
  • Say which delays are counted in the check and which are not
  • Choose between a max delay and the other ways to constrain a path

The Commands

Both commands take a time in nanoseconds and a path specification like the one of a false path:


set_max_delay 0.5 -from [get_ports a] -to [get_ports z]
set_min_delay 0.6 -from [get_ports a] -to [get_ports z]
  • set_max_delay gives the largest delay that the path may have. It replaces the setup check of the path.
  • set_min_delay gives the smallest delay that the path must have. It replaces the hold check of the path.

The path can be given with -from, -to and -through, in the same way as for a false path.

How the Check Changes

Without the command, the setup check of the path from the input a to the output z is a check against the clock. The data arrives at 0.4 + 0.1674 = 0.5674 ns, the output delay of 0.4 ns is subtracted from the clock edge at 2.0 ns, and the slack is 1.0326 ns.

With set_max_delay 0.5, the clock edge is replaced by the number that you gave. The required time becomes 0.5 ns minus the output delay of 0.4 ns:

Output
   0.4000    0.4000 v input external delay
   0.0000    0.4000 v a (in)
   0.1674    0.5674 v _2_/X (sky130_fd_sc_hd__or2_0)
   0.0000    0.5674 v z (out)
             0.5674   data arrival time

   0.5000    0.5000   max_delay
   0.0000    0.5000   clock reconvergence pessimism
  -0.4000    0.1000   output external delay
             0.1000   data required time
            -0.5674   data arrival time
            -0.4674   slack (VIOLATED)

Two things are worth noticing. The row max_delay takes the place of the clock edge row. The clock period is no longer part of the path. But the input delay and the output delay are still counted. So the number that you write must include the time that the outside world uses. In this example, the 0.5 ns is a budget for the whole path from the pin a to the pin z including the 0.4 ns of the output delay, and the arrival time includes the 0.4 ns of the input delay. For this reason, a max delay of 0.5 ns is violated, even though the OR gate takes only 0.1674 ns.

The Min Delay

The minimum delay works in the same way for hold. With set_min_delay 0.6, the hold required time is the number that you gave, minus the output delay. The path from a to z has a hold arrival time of 0.4522 ns and a required time of 0.6 - 0.4 = 0.2 ns:

Output
   0.4000    0.4000 ^ input external delay
   0.0000    0.4000 ^ a (in)
   0.0522    0.4522 ^ _2_/X (sky130_fd_sc_hd__or2_0)
             0.4522   data arrival time

   0.6000    0.6000   min_delay
  -0.4000    0.2000   output external delay
             0.2000   data required time
             0.2522   slack (MET)

The hold slack is 0.4522 - 0.2 = 0.2522 ns. The setup side of the same path was not changed by set_min_delay, so it keeps its slack of 1.0326 ns.

When to Use Them

  • For a path between two points that have no useful clock relationship, such as a combinational path in a block that is checked on its own.
  • For a path that must be fast for a reason that is not the clock, for instance a handshake or an asynchronous signal that has a timing requirement in nanoseconds.
  • As a budget when a design is divided into blocks, and each block gets its share of the delay.

If a path is launched and captured by clocks, and the clock gives the answer you want, do not use a max delay. A clock-based check is more accurate, because it also accounts for the clock arrival times, the uncertainty and the skew. A max delay replaces these with a single number.

Common Mistakes

Mistake #1: Forgetting that the external delays still count

If the path starts at a port with an input delay and ends at a port with an output delay, both are part of the check. A max delay equal to the logic delay is violated by the sum of the two external delays.

Mistake #2: Setting a max delay on a path that has a multicycle path as well

When both exceptions apply, the max delay wins for setup, and the multicycle path still moves the hold check. Exception Precedence and Common Pitfalls shows the result of this combination. Check the report of the path.

Quick Check: A path has an arrival time of 1.0 ns, a max delay of 1.5 ns and no output delay. What is the setup slack?

The required time is 1.5 ns, so the slack is 1.5 - 1.0 = 0.5 ns, which is met.

Practice Exercise

Challenge: Find the Right Number

Use the sta_demo design with the basic constraints. Add a max delay on the path from a to z:


set_max_delay 0.5 -from [get_ports a] -to [get_ports z]

Find the slack. Then calculate the smallest max delay value for which the path is met, and check it.

Open the ready-made example in the lab, run synthesis, and then run STA. Editing constraints.sdc and re-running only STA, and choosing another library or corner, are PRO features.

Hint

The arrival time is 0.5674 ns and the output delay is 0.4 ns. The required time is the max delay minus the output delay.

Solution

The slack is (0.5 - 0.4) - 0.5674 = -0.4674 ns, violated. The path is met when the max delay minus 0.4 is at least 0.5674, which means a max delay of at least 0.9674 ns. This is the same as the smallest clock period of this path from Combinational Feedthrough Paths, because both include the input delay, the gate delay and the output delay.

Summary

  • set_max_delay and set_min_delay state a delay limit for a path directly, in nanoseconds.
  • The number replaces the clock edge in the setup or hold check, so the clock period is not used for that path.
  • The input delay and the output delay are still counted, so the number must include them.
  • A max delay replaces the setup check and a min delay replaces the hold check.
  • Use them for paths without a useful clock relationship, or for budgets. Prefer the clock-based check when the clocks describe the requirement.
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