Data-to-Data Checks

Setup and hold compare a data signal with a clock edge. Sometimes the requirement is different: one data signal has to arrive before or after another data signal, and no clock edge is involved. An enable that must be stable before a select signal changes is a typical example. For these cases, STA has the data-to-data check. This article explains what it compares, how to write it, and how the report looks.

7 min read | Intermediate

What You'll Learn

• Explain when a requirement between two data signals is needed
• Use set_data_check to set a setup and a hold relation between two pins
• Say which pin is the reference and which one is constrained
• Read a data-to-data check in a report

Two Signals, No Clock

A normal check has a data pin and a clock pin. A cell that checks the timing between two data pins has none. Examples from real designs:

• A multiplexer whose select signal must be stable before its data inputs change, to avoid a glitch at the output.
• A pair of signals of a handshake, where a request must arrive some time before the data that belongs to it.
• A cell in the library with a check between two data pins, for example a pad or a custom cell. The library then holds the check, and STA makes it automatically.

For the cases that are not in the library, you describe the requirement yourself. In the Liberty file, such a check is a timing group with a data pin as the related pin. In the constraints, it is set_data_check.

The Command

The command names a reference pin and a constrained pin. The constrained pin has to arrive a given time before the reference pin, for setup, or after it, for hold:

set_data_check -from [get_pins _7_/Q] -to [get_pins _4_/B] -setup 0.1 -clock clk

• -from is the reference pin. Its data is the one that the other pin is compared with.
• -to is the constrained pin. Its data has to meet the relation.
• -setup 0.1 says that the constrained data has to arrive 0.1 ns before the reference data. A -hold value gives the minimum distance after it.
• -clock says which clock the data check is related to.

A Report

In the demo circuit, the XOR gate _4_ has the input B connected to the input port c, and the input A connected to the flip-flop _7_. The data check says that c has to arrive at the XOR gate 0.1 ns before the data of the flip-flop _7_. The setup report of this check:

Startpoint: c (input port clocked by clk)
Endpoint: _4_ (falling edge-triggered data to data check clocked by clk)
Path Type: max

   0.0000    0.0000   clock clk (rise edge)
   0.4000    0.4000 ^ input external delay
   0.0000    0.4000 ^ c (in)
   0.0000    0.4000 ^ _4_/B (sky130_fd_sc_hd__xor2_1)
             0.4000   data arrival time

   0.0000    0.0000   clock clk (rise edge)
   0.0000    0.0000 ^ _7_/CLK (sky130_fd_sc_hd__dfxtp_1)
   0.2874    0.2874 v _7_/Q (sky130_fd_sc_hd__dfxtp_1)
  -0.1000    0.1874   data check setup time
             0.1874   data required time
            -0.4000   data arrival time
            -0.2126   slack (VIOLATED)

The first part is the arrival of the constrained data: the input c arrives at 0.4 ns. The second part is the reference: the data of the flip-flop _7_ leaves at 0.2874 ns, and the setup time of 0.1 ns is subtracted, which gives the required time 0.1874 ns. The constrained data arrives 0.2126 ns too late, so the check is violated. The endpoint is described as data to data check, which is how you recognize it in a report. In the summary it appears as the pin _4_/B:

max_delay/setup group clk
_4_/B (sky130_fd_sc_hd__xor2_1)         0.1874    0.4000   -0.2126 (VIOLATED)

How It Differs From a Normal Check

• The required time comes from the arrival time of a data signal, not from a clock edge. If the reference data changes, the required time moves with it.
• The clock only plays the role of the launching clock of both signals.
• Both signals must be timed correctly. A data check between two unconstrained signals is not checked.

A data check is a requirement that you put into the design. STA does not know whether it is needed, and it does not tell you if a requirement is missing. The designer of the logic has to know it.

Hold and Other Options

The command also takes -hold for the minimum distance after the reference data, and the options -rise and -fall that give a different value for each transition of the constrained or of the reference signal. The two relations do not have to be given together. A designer who only cares that an enable arrives before a select signal writes the setup relation alone. The relation is a constraint of the design, not a property of the library cells, so it should be listed in the documentation of the interface, with the reason, in the same way as an exception.

Common Mistakes

set_data_check -from [get_pins _7_/Q] -to [get_pins _4_/B] -setup 0.1 -clock clk