Hand Calculating Slack

The best way to trust a timing report is to be able to reproduce its slack with a pencil. This article works through five examples on the demo circuit, one for each kind of path, and a last one that combines skew and clock uncertainty. For each example the steps are the same, and the result is checked against the tool.

9 min read | Intermediate

What You'll Learn

• Follow a fixed recipe to calculate setup and hold slack by hand
• Calculate the slack of register-to-register, input and output paths
• Combine clock skew and clock uncertainty in one calculation
• Check a hand result against a report and explain a difference of the last digit

The Recipe

Use these five steps for every check:

1. Draw the path and note the startpoint and the endpoint.
2. Calculate the data arrival time: the launch clock arrival (or the input delay) plus all the delays on the way. Use the largest delays for setup and the smallest for hold.
3. Calculate the data required time: the capture clock edge, plus the clock latency, minus the setup time (or plus the hold time), and with the uncertainty (or the output delay) applied.
4. Subtract: required minus arrival for setup, arrival minus required for hold.
5. Decide: zero or more is met.

The demo circuit has a clock period of 2.0 ns, an input delay and an output delay of 0.4 ns, and ideal clocks. The flip-flop _7_ is called r1 and _6_ is called r2.

Example 1: Register to Register, Setup

The path goes from r1 through the XOR gate to r2. The delays are: clock to output of r1, 0.2874 ns, and the XOR gate, 0.1450 ns. The setup time of r2 is 0.1174 ns.

The tool shows 0.4323 for the arrival and 1.4502 for the slack. The sum 0.2874 + 0.1450 is 0.4324 when you add the rounded numbers. The tool keeps more digits internally, so a difference of 0.0001 in the last digit is normal.

Example 2: Register to Register, Hold

Hold uses the smallest delays: 0.3058 ns for a rising output of r1 and 0.0599 ns for the falling output of the XOR gate. The hold time of r2 is -0.0583 ns, and both clocks are at time 0.

Subtracting a negative number adds. A negative required time is normal for hold.

Example 3: Input to Register

The path starts at the input c. The data arrives 0.4 ns after the clock edge because of the input delay, then passes the XOR gate (0.1176 ns for the slowest edge) and reaches r2.

This is the slack that the report shows for the data pin of r2 in the summary, because it is the worst of the two paths that end there. The other path, from r1, has 1.4502 ns.

Example 4: Register to Output

At an output port the required time is the clock edge minus the output delay. The path from r1 goes through an AND gate (0.0898 ns) to the output y. The rising output of r1 takes 0.3058 ns.

Example 5: Input to Output

A path from input a to the output z through an OR gate has no flip-flop. It pays the input delay and the output delay out of the same period. The OR gate takes 0.1674 ns.

This is the worst setup slack of the whole design, because the two external delays use 0.8 ns of the 2.0 ns period before the OR gate even starts.

Example 6: Skew and Uncertainty Together

Now repeat the register-to-register checks with three changes: the capture clock is 0.3 ns late, the setup uncertainty is 0.2 ns and the hold uncertainty is 0.1 ns. The constraints are:

set_clock_latency 0.3 [get_pins _6_/CLK]
set_clock_uncertainty -setup 0.2 [get_clocks clk]
set_clock_uncertainty -hold  0.1 [get_clocks clk]

The diagram shows the effect of the uncertainty on the capture clock edge: for setup it takes the edge earlier, and for hold it takes the edge later. With the skew of 0.3 ns added to both, the numbers are:

The tool agrees: a setup slack of 1.5502 ns and a hold slack of 0.0241 ns. The hold check is close to failing, because skew and uncertainty both make it harder. Increase the skew a little more and it would fail while the setup check still had more than 1.5 ns of margin.

Common Mistakes

create_clock -name clk -period 1.2 [get_ports clk]
set_output_delay 1.5 -clock clk [get_ports y]