STA Interview Questions

Static timing analysis is a standard topic in interviews for physical design, synthesis, verification and RTL roles. The questions below cover the whole tutorial, from the definition of slack to crosstalk and sign-off. Each answer is short enough to say in an interview, and the numbers come from the OpenSTA runs of this tutorial, so you can reproduce them in the lab and quote them with confidence.

14 min read | Intermediate

What You'll Learn

• Answer the basic STA questions about paths, slack, setup and hold in a few clear sentences
• Explain clocks, constraints and exceptions, with the risks of each exception
• Discuss corners, variation and signal integrity with real numbers as examples
• Describe how a failing path is analyzed and fixed

The Basics

1. What is static timing analysis, and how is it different from simulation?

STA checks every timing path of a design against its constraints, using the cell delays of the library and the delays of the wires. It does not need input vectors, so it covers all paths, not only the ones that a test exercises. A simulation checks the function for the inputs that are applied. STA checks the timing for all of them, but it knows nothing about the function.

2. What are the four types of timing path?

Input port to register, register to register, register to output port, and input port to output port. A path starts at a clock pin or an input port, and ends at a data pin of a register or an output port.

3. What is slack?

Slack is the margin of a timing check: the required time minus the arrival time for setup, and the arrival time minus the required time for hold. A positive slack means the check is met, and a negative slack is a violation. In the demo circuit, the path from input a to output z has an arrival of 0.5674 ns and a required time of 1.6000 ns, so the setup slack is 1.0326 ns.

4. What do WNS and TNS mean?

WNS is the worst negative slack, the most negative slack in the design (0 if there is no violation). TNS is the total negative slack, the sum of the negative slacks of all failing endpoints. The UART at 3.4 ns and the slow corner has a WNS of -0.32 ns and a TNS of -2.42 ns, which shows that more than one endpoint fails.

Setup, Hold and Clocks

5. Write the setup check.

The data launched at one edge must arrive before the next capture edge, minus the setup time of the capture flop: launch clock latency + clock-to-Q + data path delay <= capture clock latency + clock period - setup time - uncertainty. The clock period is in the equation, so a slower clock fixes a setup violation.

6. Write the hold check.

The new data must not arrive too soon after the capture edge: launch clock latency + clock-to-Q + data path delay (earliest) >= capture clock latency + hold time. The clock period is not in the equation, so slowing the clock does not fix a hold violation. A hold violation exists in every chip made from that design, and cannot be removed by running it more slowly.

7. Which check do you fix first, and why?

Hold is usually fixed late in the flow, after the clock tree is built, because its value depends on the real clock skew. Setup is worked on throughout. Fixing hold with delay cells costs setup slack, so the order in the final steps is to fix hold, and then check that setup still passes. In an example of the tutorial, a delay cell took the hold slack from -0.0904 ns to +0.4330 ns, and the setup slack from 2.0200 ns to 1.4801 ns.

8. What does clock skew do to setup and hold?

A capture clock that arrives later than the launch clock (positive skew) gives the data more time, which helps setup and hurts hold. An earlier capture clock does the opposite. In the demo circuit, delaying the capture clock by 0.1 ns changed a setup slack of -0.0585 ns into +0.0415 ns, and took 0.1 ns from the hold slack.

9. What is the difference between clock latency and clock uncertainty?

Latency is the delay of the clock from its source to a register pin. Before the clock tree exists, it is ideal (zero). Uncertainty is a margin that is taken from the setup check (and a separate value can be set for hold) for jitter and for the inaccuracy of the early estimates. It does not delay the clock, it only makes the checks stricter.

10. When do you need a generated clock?

When a clock is made from another clock by logic, for example by a divider or a register that toggles, and STA cannot find out by itself that the new signal is a clock with a related frequency. create_generated_clock tells STA the source, the division and the waveform, so that paths between the two clocks are checked with the right edge relation.

11. What is a virtual clock?

A clock that exists in the SDC but not on any pin of the design. It is used as the reference for input and output delays when the data comes from or goes to a block that is clocked outside this design, or when the external clock has a different latency than any clock inside.

Constraints and Exceptions

12. What do the input delay and the output delay mean?

The input delay is the time between the clock edge and the arrival of the data at the input port, which is the share of the period that the outside logic has used. The output delay is the time that the outside logic needs after the data leaves the port, until its own capture clock edge. For the UART of the tutorial, both are 2.0 ns at a 10 ns clock, and the remaining 8 ns belong to the paths inside the block.

13. A design has a good worst slack but you suspect the constraints are incomplete. What do you check?

Run check_setup -verbose. It lists the inputs without an input delay, the outputs without an output delay, the registers without a clock and the unconstrained endpoints. In the UART, a run with only the clock showed a worst slack of 8.2477 ns, which hid the real worst slack of 7.0819 ns that appeared when the port delays were added.

14. What is a false path? Give an example and a risk.

A path that exists in the netlist but never carries a signal that matters for timing, so it is excluded from the checks. An example is a static configuration register that is written once at start-up. The risk is that a path is excluded that is in fact active: it is never checked, and the design can fail in the chip. A false path needs a written reason.

15. What is a multicycle path?

A path whose data is allowed more than one clock period to arrive, because the design only uses it every N cycles. Setting the setup multiplier to N moves the capture edge N periods later. The hold check must then be moved back by N-1 periods, or the hold check would be tested against the wrong edge and be too strict.

16. What are recovery and removal checks?

They are the setup and hold checks of the release of an asynchronous set or reset. Recovery: the reset must be released at least the recovery time before the next clock edge. Removal: it must be released at least the removal time after the clock edge. In the UART at the slow corner, the removal time of the flip-flop is 0.6148 ns, and a reset that arrives at 0.5000 ns has a removal slack of -0.1148 ns.

17. How do you constrain an external asynchronous reset that goes through a synchronizer?

The external port is not related to the clock, so a timing check from it has no meaning. It is declared a false path (set_false_path -from [get_ports rst_n]), and the safe release of the reset is the job of the two-flop synchronizer. The path from the synchronizer to the rest of the design is a normal recovery and removal check, which is met by the clock-to-Q delay of the synchronizer flop.

Corners, Variation and Signal Integrity

18. Which corner do you use for setup and which for hold?

Setup uses the slow process, the lowest voltage and (in most technologies) the highest temperature, with the slowest wires. Hold uses the fast process, the highest voltage and the lowest temperature, with the fastest wires. In the demo circuit with no wires, the worst setup slack is 0.7856 ns at the slow corner against 1.0994 ns at the fast one, and the worst hold slack is 0.2681 ns at the fast corner against 0.5966 ns at the slow one.

19. Why does adding the wire parasitics help hold but hurt setup?

The wires add delay to the data. Later data has less time before the capture edge (setup gets worse) and arrives further from the capture edge of the previous cycle (hold gets better). In the demo, reading the parasitics of one net lowered the slow corner setup slack from 0.7856 to 0.6380 ns, and raised the fast corner hold slack from 0.2681 to 0.3290 ns.

20. What is on-chip variation and how is it handled?

The cells and wires of one chip are not exactly equal, even at one corner. To stay safe, the checks use a late (slower) derate on the launch path and data path and an early (faster) derate on the capture path for setup, and the opposite for hold. Derates are one number for all cells. Advanced on-chip variation (AOCV) and statistical methods use smaller derates that depend on the depth of the path and its distance, because the random differences average out over long paths.

21. What is common path pessimism removal (CPPR)?

The launch clock path and the capture clock path share a part, the clock tree up to the point where they split. On-chip variation derates would make the shared cells both slow and fast at the same time, which cannot be real. CPPR adds back the difference of the delays on that shared part, so that the check is not pessimistic for it.

22. How does crosstalk change timing?

A neighbouring net (the aggressor) that switches at the same time as the victim changes the delay of the victim. If the aggressor switches in the opposite direction, the victim is slower (a danger for setup). If it switches in the same direction, the victim is faster (a danger for hold). In the demo, the victim edge arrives at 0.6561 ns with a helping aggressor, 0.7224 ns when the aggressor is quiet and 0.7961 ns when it works against it. Timing windows tell the tool which aggressors can really switch at the same time.

23. What is graph-based and path-based analysis?

Graph-based analysis keeps one value per pin (the worst arrival, the worst slew) and is fast, but it can be pessimistic because every path through a pin uses the worst slew of the pin, even if it did not come from the path that caused it. Path-based analysis recalculates one path with its own values. In the demo, a slow input edge on c reduced the graph-based slack of a path that does not pass through c from 1.4502 to 1.3992 ns, and the path-based result gives the correct 1.4502 ns back.

Closure and Practice

24. A path has a violation. How do you decide what to change?

Read the cells on the path: the delay, the load and the output slew of each. A cell with a large load and a slow output edge needs more drive, with a stronger cell or a buffer. A cell with a small load and a large delay needs a different structure with fewer inputs or a different gate. A long wire needs a buffer or a better placement. A small violation with neighbours that have slack can use useful skew. Every change needs a new run at all the corners, as it can move the problem to another path or another check.

25. How can you reduce the logic depth in RTL?

Register the result of a long compare so that the logic that uses it starts at a flip-flop. Split wide counters into smaller ones. Pipeline arithmetic. In the UART of the tutorial, two 5-bit counters (28 x 31 = 868 cycles) and a registered tick changed the worst path from five cells to four, and the slow corner setup slack from -0.3165 ns to +0.0923 ns, with the same output at every clock cycle.

26. How do you estimate the maximum frequency of a design from a timing report?

For paths between registers, the setup slack changes by the same amount as the clock period. The smallest period is about the period of the run minus the worst setup slack, as long as the worst path stays the same. A UART with a worst slack of +0.0923 ns at 3.4 ns can run at about 3.31 ns. Confirm with a new run at that period, because another path may become the worst.

27. What can STA not check?

The function of the design, and signals that cross between clocks with no fixed relation (clock domain crossing). STA can check that a synchronizer exists in the netlist only if you look for it, and it does not check that the data is transferred correctly. Those need simulation, equivalence checking and CDC tools.

28. What changes in the timing report between before and after clock tree synthesis?

Before, the clock is ideal and the line clock network delay (ideal) shows 0.0000 for all registers. After, the clock is propagated, and the real delays of the clock tree are added to the launch and capture paths, which creates skew. This is why hold violations appear mostly after clock tree synthesis, and why the same design can look much better before it.

Practice Exercise

Summary

• Know the four path types, the setup and hold equations, and the meaning of slack, WNS and TNS.
• Setup depends on the clock period and hold does not, which decides what each fix can be.
• Constraints define what STA checks. check_setup shows what is missing, and every exception needs a reason.
• Use the slow corner for setup and the fast corner for hold, with the matching wire parasitics.
• Variation and crosstalk change the delay of a path, and derates, CPPR and timing windows keep the analysis safe without too much pessimism.
• To fix a path, read the delay, load and slew of its cells, change what causes the delay, and run all corners again.