Standard Cell Libraries and Liberty

A standard cell library is a collection of ready-made logic gates and flip-flops that a design is built from. The Liberty file (.lib) is the data sheet of that library. It tells static timing analysis how fast every cell is, how much load every pin presents, and what every flip-flop requires.

Think of the library as the parts catalogue of a hardware shop. Every part has a data sheet with its size, its speed and what it needs. A designer builds the chip from catalogue parts, and STA reads the same data sheets to know how fast each part is.

7 min read | Intermediate

What You'll Learn

• Describe what a standard cell library contains and how cell and corner names are built
• Identify the main parts of a Liberty file: header, operating conditions, cells, pins and timing groups
• Explain pin capacitance and how it adds up to the load on a net
• Read the units and the key attributes of a real cell

What a Standard Cell Library Is

When synthesis turns your RTL into gates, it does not draw transistors. It picks cells from a library. Each cell is a small pre-designed block, such as an AND gate, an XOR gate or a D flip-flop, with a known layout and known electrical behavior.

Most functions come in several sizes. The names show it:

The four AND2 cells of the library used in ChipVerify Lab are a good example. A larger variant can drive a bigger load, but it takes more area:

The lab offers several libraries, such as high density (hd), high speed (hs) and low leakage (ls). The examples in this series use the high-density library, sky130_fd_sc_hd, which has 428 cells. Each library exists in several corners. A corner is a set of operating conditions: process, voltage and temperature. A later article explains corners in detail.

What Liberty Is

Liberty is a text format. An STA tool reads the Liberty file together with the netlist and the constraints. For every cell it holds the area, the function, the pins, the capacitance of each pin, and a timing group for every timing arc. This is what a Liberty file looks like, reduced to its structure:

The file is a tree. A library holds cells, a cell holds pins, and an output pin holds timing groups. Each timing group is one arc of the timing graph you met earlier, together with its delay tables.

The Header: Units and Operating Conditions

The first lines of the file set the units for every number below them. In this library:

time_unit : "1ns";
capacitive_load_unit(1.0000000000, "pf");
delay_model : "table_lookup";

So all times are in nanoseconds and all capacitances are in picofarads. The line delay_model : "table_lookup" says that delays are stored in tables. The next article explains them.

The operating_conditions group states the voltage and temperature the numbers were calculated for. For tt_025C_1v80 they are 1.8 V and 25 degrees C.

Pin Capacitance

Every input pin of a cell is a small capacitor. When a net drives several input pins, their capacitances add up, and that sum is the load the driving cell has to charge. A bigger load means a slower driver, so STA needs these values.

Pin capacitance in the library is given for rising and for falling input edges. Output pins normally have no capacitance of their own, because the load of an output is made of the inputs and wires it connects to. In the demo circuit, the output Q of r1 drives the XOR and the AND gate:

The sums, 0.0062 pF for a rising edge and 0.0058 pF for a falling edge, are exactly what the Cap column of the timing report shows for _7_/Q.

Reading One Cell

For the and2_0 cell the data that matters is short:

• Pin A and pin B are inputs with capacitances of about 0.0016 pF.
• Pin X is the output. Its function is (A&B).
• max_capacitance of X is 0.108958 pF, the largest load the manufacturer allows this output to drive.
• One timing group for the arc from A to X and one for B to X.

Common Mistakes

set_load 0.02 [get_ports z]