When a path fails, the tools and the designer have a small set of moves to fix it. Each move trades one thing for another: speed for area, speed for power, one path's slack for another's. This article lists the main techniques, sizing, buffering, restructuring, threshold voltage swapping and useful skew, shows the effect of two of them with real numbers, and gives a rule for choosing among them.
9 min read | Intermediate
What You'll Learn
- Name the main optimization techniques and the price of each
- Read the cap, slew and delay of a cell to decide which technique fits
- Calculate the benefit of a buffer in front of a heavy load
- Explain threshold voltage swapping and useful skew
Read the Path First
The report of the failing path tells which technique to try. Look at each cell on the path:
- A large delay with a large load (the
Capcolumn) and a slow output slew means that the cell is struggling with the load. The fix is more drive: a stronger cell, or a buffer. - A large delay with a small load means that the cell is slow by itself. A bigger cell does not help. The fix is a different structure: fewer inputs or a different gate type.
- A normal cell on a long wire. The fix is on the wire: a buffer in the middle, or moving the cells.
- A path that fails by a small amount while its neighbours have slack. The clock can help.
Sizing
A library has several sizes of each gate. A larger one drives more current. It reduces the delay when the load is large, and it increases the load on the cell before it. The price is area and power. The article about timing-driven synthesis showed that it can also make things worse: the larger OR cells there had delays of 0.5945 ns and 0.4639 ns against 0.4542 ns for the small one, because the load was light.
Buffering
A buffer isolates a heavy load from a weak driver. Take a flip-flop that drives a large capacitance of 0.15 pF, for example a long wire with many loads, into the data pin of the next flip-flop. With a 1.0 ns clock and an input delay of 0.2 ns:
| Version | Load seen by the flip-flop (pF) | Delay of the driving stage (ns) | Setup slack (ns) |
|---|---|---|---|
| flip-flop drives the load directly | 0.1517 | 1.2419 (clock to Q, slew 1.4018) | -0.4796 |
flip-flop, then buf_4 drives the load | 0.0025 | 0.2811 + 0.3732 (buffer) | +0.1986 |
The flip-flop alone needs 1.2419 ns to charge the load, and its output slew of 1.4018 ns also increases the setup time of the capture flip-flop from 0.1471 ns to 0.2377 ns. With the buffer, the flip-flop sees only 0.0025 pF and takes 0.2811 ns, and the buffer, a cell with a strong output stage, drives the big load in 0.3732 ns with a slew of 0.4165 ns. The total is 0.6543 ns instead of 1.2419 ns, and the slack goes from -0.4796 ns to +0.1986 ns. Buffers are also used on long wires, where they cut the resistance and the capacitance in two, as described in the chapter about wires.
Restructuring
When the delay of a cell is mostly its own, another arrangement of gates is the answer. Replacing the 4-input OR cell of the example by two NOR gates and one NAND gate moved the setup slack from -0.0585 ns to +0.2339 ns, at about 5 percent more area. The synthesis tool does this in its own steps. In the later steps, restructuring is harder, because it changes the netlist and the placement, so it is used in an engineering change.
Threshold Voltage Swapping
Many technologies offer the same cell in several versions with a different threshold voltage of the transistors. A low threshold cell is faster and leaks more current. A high threshold cell is slower and leaks less. A flow for a block with low activity, where leakage is a large part of the power, starts with high threshold cells and swaps the cells on the critical paths to faster ones. A flow for a block with high activity does the opposite: it starts with fast cells to meet timing, and then swaps the cells on the paths that have slack to high threshold cells, because a design made only of slow cells needs more and larger cells and can use more total power. The cell has the same footprint, so nothing moves on the chip, and the swap is the least disruptive timing fix. The price is leakage power. The libraries used in this tutorial have one threshold version of each cell, so there is no numeric example here. The method is the same as for sizing: swap the cell in the netlist, and run STA again.
Useful Skew
A path that fails by a little can borrow time from its neighbours by delaying its capture clock. In the example of the article about clock skew, 0.1 ns of delay changed a setup slack of -0.0585 ns into +0.0415 ns, and took the same 0.1 ns from the next stage and from the hold slack of the path. It costs no cell area, but it needs the clock tree to realize the delay, and it moves the problem to the neighbours.
Comparing the Techniques
| Technique | Helps when | Price | Side effects to check |
|---|---|---|---|
| Sizing up | large load | area, power | load on the previous cell |
| Buffering | heavy load or long wire | area, power, one more stage | hold, slew of the buffer |
| Restructuring | slow cell with a small load | area, effort | other paths through the same gates |
| Low threshold swap | moderate violation | leakage power | hold, power budget |
| Useful skew | small violation, neighbours with slack | none in area | neighbours, hold |
| Slower clock | nothing else works | performance | none |
The Order of Preference
A common order is to start with the techniques that change the least: a threshold swap or sizing for small violations, buffering for loads and wires, useful skew where there is spare time, and restructuring for the paths that need it. Every change is checked with a new STA run, because a change of one cell moves the numbers of the others.
Common Mistakes
Mistake #1: Applying one technique to every violation
Sizing everything, or swapping everything to low threshold, uses up area and power budgets on paths that did not need it. Match the technique to the cause in the report.
Mistake #2: Fixing a path and not checking the cell before it
A larger cell has a larger input capacitance, and the cell before it gets slower. A fix can move the violation one stage back.
Quick Check: A cell has a large load and a slow output slew. Which technique fits best?
More drive for that net: a stronger cell, or a buffer between the cell and the load.
Practice Exercise
Challenge: Is the Buffer Worth It?
This is a pencil and paper exercise with the table above. The buffer version has a total delay of 0.2811 + 0.3732 ns for the two stages, and the setup time of the capture flip-flop is 0.1471 ns, with an input delay of 0.2 ns, a clock of 1.0 ns and a launch edge at 0. Check the setup slack. Then calculate how much slower the data would be if the buffer were replaced by a buffer that takes 0.60 ns.
Hint
The arrival time is the sum of the two stages. The required time is the clock period minus the setup time.
Solution
The arrival time is 0.2811 + 0.3732 = 0.6543 ns and the required time is 1.0 - 0.1471 = 0.8529 ns, so the slack is 0.8529 - 0.6543 = 0.1986 ns, as in the table. With a buffer that takes 0.60 ns, the arrival time is 0.8811 ns, which is later than 0.8529 ns by 0.0282 ns, so the slack is -0.0282 ns and the path fails. The buffer is worth it only while its delay stays below 0.5718 ns.
Summary
- Read the cap, slew and delay of each cell on the failing path before you choose a technique.
- Sizing and buffering help against loads and wires. They do not help a cell that is slow by itself.
- A
buf_4in front of a 0.15 pF load changed a setup slack of -0.4796 ns into +0.1986 ns. - Restructuring replaces a slow cell by faster gates, as in the OR cell example.
- Low threshold cells are faster and leak more. Useful skew costs no area and moves the problem to the neighbours.
- Re-run STA after every change and check hold and the neighbouring paths.
