Physical Design Interview Questions

What are the main steps from netlist to GDSII?

1. Floorplan: die and core size, I/O pins, macro placement, rows and blockages.
2. Power planning: rings, straps and rails, plus tap and endcap cells.
3. Placement: global placement, timing-driven repair, legalization and detailed placement.
4. Clock tree synthesis: build the clock network and fix hold.
5. Routing: global routing, then detailed routing, then post-route optimization.
6. Sign-off: parasitic extraction and STA at all corners, DRC, LVS, antenna, IR drop and electromigration, then GDSII stream-out.

Read more on The RTL-to-GDSII Flow.

What inputs does a physical design flow need?

• The gate-level netlist from synthesis.
• Timing constraints (SDC).
• The technology LEF: routing layers, directions, pitches, widths, spacings and vias.
• The cell LEF: each cell's size, pins and obstructions.
• Liberty timing and power libraries for each corner.
• Parasitic extraction rules, and the DRC and LVS rule decks from the PDK.

The LEF files only describe what the tools need for placement and routing; the real transistor layout of each cell is in its GDS, which is merged at stream-out.

Read more on Physical Design Inputs and Outputs.

What is utilization, and how do you choose it?

Utilization is the fraction of the core area covered by standard cells and macros. A low utilization wastes area and makes wires longer. A high utilization leaves too little room for buffers added during optimization and for routing, which leads to congestion and timing problems.

Typical starting points are 50 to 70 %, lower for designs with heavy routing such as crossbars, higher for regular datapaths. The right value is found by trying the flow and looking at congestion and timing after placement and routing.

Read more on Die, Core and Utilization.

How do you place macros in a floorplan?

• Place macros near the edges or corners of the core, leaving the centre for standard cells.
• Orient macro pins toward the logic they connect to, and keep macros that talk to each other close.
• Leave channels between macros wide enough for routing and power, and add halos or blockages around them.
• Follow the data flow of the design, guided by the connectivity between macros, I/Os and logic.

Poor macro placement shows up later as congestion near the macros, long wires and timing violations that placement cannot fix.

Read more on Macro Placement.

Why does a power grid need straps on upper metal layers?

Standard cells connect to thin metal 1 rails along each row. Those rails have high resistance over long distances and need to be fed from somewhere. Straps on upper, thicker layers distribute the current across the core with low resistance, and connect to the rails through via stacks at regular intervals.

Without enough straps, the voltage drop along the rails (IR drop) slows down cells far from the supply, and the current density in thin wires can exceed electromigration limits.

Read more on Rails, Rings and Straps.

What are tap cells, endcaps and decap cells for?

Tap cells connect the n-well to VDD and the substrate to VSS at regular intervals, which prevents latch-up in libraries whose cells do not have their own well ties. Endcap cells sit at the ends of each row to terminate the wells and diffusion properly and meet design rules at the row boundary.

Decap cells are capacitors between VDD and VSS placed in empty space. They supply charge locally when many cells switch at once and reduce dynamic voltage droop.

Read more on Tap Cells, Endcaps and Decaps.

What happens during placement?

Global placement spreads cells over the core to minimize total wire length, while limiting the density in each region, so the cells overlap and are not yet on legal sites. Timing-driven and congestion-driven placement adjust the result to shorten critical nets and avoid crowded areas.

Legalization then snaps every cell onto a row site with no overlaps, moving each cell as little as possible, and detailed placement swaps and shifts neighbouring cells to improve wire length further. Buffering and sizing repair are run in between to fix slew, capacitance and timing.

Read more on Global Placement and Legalization and Detailed Placement.

What are the goals of clock tree synthesis?

• Deliver the clock to every sink with low skew between related flops.
• Keep the insertion delay (latency) reasonable.
• Meet maximum transition and capacitance limits on the clock nets.
• Keep clock power and area low, since the clock tree toggles every cycle.

The tree is built from clock buffers or inverters, often with non-default routing rules (wider spacing, shielding) to reduce crosstalk and variation.

Read more on Why Clock Trees and CTS in OpenROAD.

Why is hold fixed after CTS and not before?

Before CTS the clock is ideal: it arrives at every flop at the same time, so the skew used in the hold check is only an estimate. Hold violations depend strongly on the real skew between launching and capturing flops.

After CTS the real clock tree delays are known, so hold can be measured correctly and fixed with delay buffers where needed. Fixing hold before CTS would insert buffers against a skew that does not exist yet.

Read more on Skew, Useful Skew and Hold.

What is the difference between global and detailed routing?

Global routing divides the chip into a grid of tiles and plans which tiles each net passes through, balancing demand against the available tracks. It reports congestion as overflow where demand exceeds capacity.

Detailed routing then assigns exact tracks, wires and vias inside each tile while obeying all spacing and width rules. Zero global overflow does not guarantee a clean detailed route, because local pin access and design rules can still cause violations.

Read more on Global Routing and Congestion and Detailed Routing.

What causes antenna violations, and how are they fixed?

During manufacturing, metal layers are etched with plasma, which collects charge on exposed wires. If a long wire connects only to a transistor gate before the higher layers that link it to a diffusion are built, the charge can discharge through the thin gate oxide and damage it. The antenna ratio is the wire area connected to a gate compared with the gate area.

Fixes are to jump to a higher metal layer near the gate so the long segment is connected later, to add an antenna diode that gives the charge a safe path, or to insert a buffer to split the net.

Read more on The Antenna Effect.

How do timing results change from placement to post-route?

Before routing, wire delays are estimated from the placement, usually with simple wire models. After routing, the real wires are extracted with their resistance, capacitance and coupling, which usually makes paths slower and can add crosstalk delay.

This is why slack is often worse after routing and why post-route optimization exists. Large differences between estimated and extracted timing point to detours from congestion, long nets or missing constraints during placement.

Read more on Parasitics After Routing and Post-Route STA.

What is an ECO?

An engineering change order is a small, targeted change made late in the flow instead of rerunning everything. A timing ECO resizes or adds a few cells to fix violations; a functional ECO changes logic after a late bug fix, often using spare cells so only some metal layers change.

After an ECO the affected areas are re-routed, and extraction, STA, DRC, LVS and equivalence checking must be run again, because a small change can still break timing or connectivity elsewhere.

Read more on ECOs After Routing.

What do DRC and LVS check?

Design rule checking (DRC) verifies that the layout geometry follows the foundry's rules: minimum widths, spacings, enclosures, densities and more, so the chip can be manufactured.

Layout versus schematic (LVS) extracts the devices and connections from the layout and compares them with the netlist, so the layout implements exactly the intended circuit. Typical LVS failures are shorts between nets, opens, missing well ties or power connections, and pin name mismatches. A design must be clean on both before tapeout.

Read more on Design Rule Checking and Layout Versus Schematic.

What is IR drop, and how is it analysed?

IR drop is the voltage lost across the resistance of the power grid when current flows through it, so cells see less than the nominal supply and become slower. Static IR drop uses average currents; dynamic IR drop uses switching activity over time and captures local droop when many cells switch together.

It is analysed at the corner with the highest current, and fixed by adding straps and vias, spreading high-activity cells, and adding decap cells. Electromigration is checked from the same current data, against the current density limits of each wire and via.

Read more on IR Drop and Power Sign-Off: IR and EM.