14 min read | Advanced Level
What You'll Learn
- Configure power-aware place-and-route flows
- Plan voltage islands and power domain placement
- Route power rails and handle multi-voltage interconnect
- Verify IR drop, electromigration, and power grid integrity
From Gates to Silicon
Your power-aware synthesis completed successfully: 2,400 isolation cells inserted, 800 retention flip-flops placed, gate-level netlist matches UPF intent. You proceed to place-and-route, expecting straightforward completion.
Three weeks later, physical design is still struggling:
- Isolation cells placed in GPU domain lose their always-on supply
- Level shifters between CPU and GPU violate max transition time
- IR drop in VDD_GPU exceeds 10% (spec: < 5%)
- Power switch placement causes 2mm detour in critical timing path
Standard place-and-route tools don't understand power domains, multiple supplies, or voltage-dependent constraints.
Physical implementation for multi-voltage designs requires power-aware P&R tools (IC Compiler, Innovus) and careful planning. Standard flows treat all cells identically, violating power intent and causing functional/reliability failures.
Power-Aware Physical Design Flow
IC Compiler Power-Aware Flow (Synopsys)
# icc2_setup.tcl - Power-aware P&R flow
# 1. Load design and UPF
read_verilog synth_netlist.v
link_design top_design
load_upf synth_netlist.upf
# 2. Load technology and physical libraries
read_ndm_libs technology.ndm
read_def floorplan.def # Pre-defined floorplan with voltage islands
# 3. Power-aware checks
check_mv_design -verbose
# Must pass: verify UPF consistency with netlist
# 4. Create power-aware placement constraints
# Group cells by power domain
create_placement_blockage -type hard \
-boundary {voltage_island_cpu} \
-name cpu_placement_region
create_placement_blockage -type hard \
-boundary {voltage_island_gpu} \
-name gpu_placement_region
# 5. Place cells with power-domain awareness
place_opt -power # Power-aware placement
# 6. Clock tree synthesis with domain-aware buffers
clock_opt -power
# 7. Route with multi-voltage awareness
route_opt -power
# 8. Verify power integrity
check_mv_design -post_route
report_power_rail_analysis
report_ir_drop
Voltage Island Planning
Voltage Island Floorplan
Group cells from same power domain into physical regions (voltage islands):
+----------------------------------------------------------------+ | TOP LEVEL (VDD_SYS = 1.8V always-on) | | | | +----------------------+ +--------------------------------+ | | | CPU Island | | GPU Island | | | | VDD_CPU = 0.8-1.0V | | VDD_GPU = 0.7-0.9V | | | | (DVFS) | | (DVFS) | | | | | | | | | | - CPU cores | | - GPU cores (64 units) | | | | - L1 cache | | - Texture units | | | | - MMU | | - Rasterizer | | | +----------------------+ +--------------------------------+ | | | | +----------------------------------------------------------+ | | | Memory Subsystem (VDD_MEM = 1.1V) | | | | - L2 cache (4x 512KB banks) | | | | - Memory controller | | | +----------------------------------------------------------+ | | | | Always-on logic: NoC, PMU, RTC (VDD_SYS, never powers down) | +----------------------------------------------------------------+ Key constraints: - Minimize wire length between communicating domains (reduce capacitance) - Place isolation/level shifter cells at domain boundaries - Route dedicated power rails to each island - Keep power switches close to their controlled domains
Floorplan Commands
# Define voltage island regions
create_voltage_area VA_CPU -power_domain PD_CPU \
-region {100 100 400 500} # x1 y1 x2 y2 in um
create_voltage_area VA_GPU -power_domain PD_GPU \
-region {450 100 850 500}
create_voltage_area VA_MEM -power_domain PD_MEM \
-region {100 550 850 800}
# Reserve space for power switches (large cells)
create_keepout_margin -type hard -outer {50 50 50 50} \
-on_ref power_switch_macro
Power Rail Routing
Multi-Voltage Power Grid
Each voltage domain requires dedicated power rails:
Metal layers allocation (typical 7-metal process): M7: VDD_SYS (top metal, widest, always-on) M6: VSS (ground, widest) M5: VDD_CPU, VDD_GPU (domain supplies, wide) M4: VDD_MEM, VDD_RET (secondary supplies, medium) M3-M1: Signal routing (narrow) Width requirements (7nm process example): VDD_SYS: 10um width (always-on, high current) VDD_CPU/GPU: 8um width (switched, DVFS) VSS: 12um width (return path for all domains) VDD_RET: 2um width (low current, always-on) Spacing requirements: VDD_CPU to VDD_GPU: 2um minimum (different voltages) VDD_CPU to VSS: 1um minimum (DC bias OK)
Power Mesh Generation
# Create power mesh for each domain
create_pg_mesh_pattern pg_top \
-layers {M7 M6} \
-tracks {M7 20 M6 20} \
-voltages {VDD_SYS VSS}
create_pg_mesh_pattern pg_cpu \
-layers {M5} \
-tracks {M5 15} \
-voltages {VDD_CPU} \
-region VA_CPU
create_pg_mesh_pattern pg_gpu \
-layers {M5} \
-tracks {M5 15} \
-voltages {VDD_GPU} \
-region VA_GPU
# Connect cells to appropriate power rails
connect_pg_net -net VDD_CPU [get_cells -hier PD_CPU/*]
connect_pg_net -net VDD_GPU [get_cells -hier PD_GPU/*]
connect_pg_net -net VDD_SYS [get_cells -hier {*iso_cell* *ls_cell*}]
Special Cell Placement
Isolation Cell Placement
Isolation cells must be placed in the parent (always-on) domain, close to domain boundaries:
# Constrain isolation cells to parent domain
set_dont_touch_placement [get_cells *iso_cell*]
# Place isolation cells at domain boundary
create_placement_guide -name iso_cells \
-cells [get_cells *iso_cell*] \
-boundary_region {interface between VA_GPU and always-on}
# Verify isolation cell supply connectivity
check_mv_design -isolation_cells
Retention Cell Placement
Retention cells need connection to both primary supply (VDD_CPU) and retention supply (VDD_RET):
# Ensure retention cells can access both supplies
set_routing_rule ret_cells \
-min_routing_layer M3 \
-max_routing_layer M5 \
-preferred_routing_layer_horizontal M4 \
-preferred_routing_layer_vertical M5
# Connect retention cells to dual supplies
connect_pg_net -net VDD_CPU [get_pins -hier */VDD -of [get_cells *ret_ff*]]
connect_pg_net -net VDD_RET [get_pins -hier */VDD_RET -of [get_cells *ret_ff*]]
IR Drop Analysis and Fixing
IR Drop Problem
Current through power grid resistance causes voltage drop:
VDD at power pad: 1.0V Current draw: 2A Power grid resistance: 50mO IR drop: V = I × R = 2A × 0.05O = 0.1V (10%!) VDD at chip center: 1.0V - 0.1V = 0.9V Impact: - Cells slow down (VDD-dependent delay) - Timing violations on critical paths - Functional failures if drop > 15%
IR Drop Analysis
# Run IR drop analysis
report_ir_drop -threshold 0.05 # Report drops > 5%
# Output:
# IR Drop Hotspots:
# Location (1200, 850): 8.2% drop (VDD_GPU)
# Peak current: 1.8A
# Grid resistance: 45mO
# Recommendation: Add decoupling caps, widen power rails
#
# Location (400, 300): 6.1% drop (VDD_CPU)
# Peak current: 1.2A
# Grid resistance: 51mO
IR Drop Fixes
- Widen power rails: Reduce resistance (R ? 1/width)
- Add decoupling capacitors: Supply local current spikes
- Add power straps: Parallel current paths reduce effective resistance
- Move power pads closer: Shorter distance = lower resistance
# Add power straps to reduce IR drop
create_pg_strap -net VDD_GPU -layer M5 \
-width 2.0 -spacing 50 -direction vertical
# Add decoupling capacitors at hotspots
insert_decap -lib_cells {DCAP_HVT_X8} \
-locations {{1200 850} {400 300}}
# Re-analyze IR drop
report_ir_drop -threshold 0.05
# After fixes: Max drop = 4.8% (PASS)
Quick Check
Q: Why does IR drop matter more in multi-voltage designs than single-voltage designs?
Show Answer
Multi-voltage designs use lower voltages (0.7-1.0V vs. traditional 1.8V), so the same absolute IR drop (e.g., 0.1V) represents a larger percentage of supply voltage. A 0.1V drop is 5.5% of 1.8V but 10% of 1.0V and 14% of 0.7V. Additionally, DVFS means timing analysis must account for worst-case IR drop at every operating point, making convergence more difficult.
Electromigration Verification
Electromigration Problem
High current density in metal wires causes atoms to migrate, eventually causing open circuits:
Current density limit (7nm, M5 copper): 2 mA/um width Power rail: 8um wide × 1.5A current = 0.19 mA/um (SAFE) Signal wire: 0.1um wide × 0.5mA current = 5 mA/um (FAIL!) Electromigration causes wire to open after 1-2 years ? field failures
Electromigration Checks
# Run electromigration analysis
check_em -verbose
# Output:
# EM Violations (3):
# Net: VDD_GPU_local_87
# Segment: (1205.3, 847.2) to (1205.3, 852.8)
# Width: 0.5um, Current: 3.2mA, Density: 6.4 mA/um (FAIL)
# Fix: Widen wire to 2um or add parallel wire
# Fix violations by widening wires
set_routing_rule high_current_nets \
-min_width 2.0 \
-nets [get_nets *VDD_GPU_local*]
Common Beginner Mistakes
Mistake #1: Placing isolation cells in powered-down domain
Symptom: X-propagation in silicon despite correct UPF.
Cause: Physical design placed isolation cells in GPU domain instead of parent.
Fix: Use placement constraints to force isolation cells into always-on regions.
Mistake #2: Insufficient power rail width
Symptom: IR drop violations, timing failures in silicon.
Cause: Default rail widths sized for single-voltage, not multi-domain current.
Fix: Calculate required width: W = I / (J_max × thickness), where J_max = current density limit.
Mistake #3: Not verifying multi-voltage timing
# WRONG: Single PVT corner
set_operating_conditions -analysis_type on_chip_variation \
-voltage 1.0
# CORRECT: Multiple corners for each DVFS operating point
set_operating_conditions -analysis_type on_chip_variation \
-voltage {1.0 0.9 0.8} \ # All DVFS voltages
-process {fast nominal slow}
Summary
In this tutorial, you learned:
- Power-aware physical design requires specialized P&R tools (ICC, Innovus) that understand UPF, multiple voltages, and domain placement
- Voltage island planning groups cells by power domain, minimizes cross-domain wiring, and reserves space for power switches
- Multi-voltage power grids require dedicated rails per domain with appropriate width (8-12um for primary supplies) and metal layer assignment
- Special cells (isolation, retention, level shifters) need careful placement: isolation in parent domain, retention with dual supply access
- IR drop analysis identifies voltage drop hotspots; fixes include wider rails, decoupling caps, power straps, and pad repositioning
- Electromigration verification ensures current density < limits (typically 2 mA/um for copper interconnect)
- Multi-voltage timing analysis must cover all DVFS operating points and worst-case IR drop scenarios
Congratulations! You've completed the comprehensive UPF tutorial series, mastering low-power design from fundamentals through physical implementation.