A set of Verilog statements are usually executed sequentially in a simulation. These statements are placed inside a procedural block. There are mainly two types of procedural blocks in Verilog - initial and always
initial [single statement] initial begin [multiple statements] end
What is the initial block used for ?
initial block is not synthesizable and hence cannot be converted into a hardware schematic with digital elements. Hence initial blocks do not serve much purpose than to be used in simulations. These blocks are primarily used to initialize variables and drive design ports with specific values.
When does an initial block start and end ?
initial block is started at the beginning of a simulation at time 0 unit. This block will be executed only once during the entire simulation. Execution of an
initial block finishes once all the statements within the block are executed.
The image shown above has a
module called behave which has two internal signals called a and b. The
initial block has only one statement and hence it is not necessary to place the statement within
end. This statement assigns the value 2'b10 to a when the initial block is started at time 0 units.
What happens if there is a delay element ?
The code shown below has an additional statement that assigns some value to the signal b. However this happens only after 10 time units from execution of previous statement. This means that a is assigned first with the given value and then after 10 time units, b is assigned to 0.
How many initial blocks are allowed in a module ?
There are no limits to the number of
initial blocks that can be defined inside a module.
The code shown below has three
initial blocks all of which are started at the same time and run in parallel. However, depending on the statements and the delays within each initial block, the time taken to finish the block may vary.
In this example, the first block has a delay of 20 units, while the second has a total delay of 50 units (10 + 40) and the last block has a delay of 60 units. Hence the simulation takes 60 time units to complete since there is atleast one initial block still running until 60 time units.
$finish is a Verilog system task that tells the simulator to terminate the current simulation.
If the last block had a delay of 30 time units like shown below, the simulation would have ended at 30 time units thereby killing all the other
initial blocks that are active at that time.
initial begin #30 $finish; end
initial block is not synthesizable.