Verilog Specify Block

Structural models, such as the simulation models of ASIC library cells, describe delays in two ways. Distributed delays are placed on the individual gates and nets inside the module, as in and #2 (y, a, b);. Module path delays describe the total delay from an input pin to an output pin, no matter which gates the signal passes through on the way. Module path delays, together with timing checks, are written in a specify block.

11 min read | Beginner Level

What You'll Learn

• What a specify block is and where it is used
• How to declare full and parallel module paths with *> and =>
• How to write edge-sensitive and state-dependent paths, and the ifnone default
• How timing checks such as $setup and $hold report timing violations

What is a specify block ?

A specify block defines the timing of a module as seen from its ports: how long each output takes to respond to a change on each input, and which timing rules the inputs must follow, such as the setup and hold times of a flip-flop. Simulators use these values to model the real timing of a cell, and the values can later be replaced by more accurate ones calculated from the chip layout.

Syntax

A specify block is written inside a module, between the keywords specify and endspecify. It can contain three kinds of items:

specify

// Checks and Statements

endspecify

• specparam declarations: named constants for delays and limits, which can only be used inside the module
• Path declarations: the delay from a source port to a destination port
• System timing checks: tasks such as $setup and $hold that report when the inputs violate a timing rule

Specify Example

The module below is a 2-input AND cell. The output rises 5 time units and falls 3 time units after a change on either input:

module example_module (
    input wire a,
    input wire b,
    output wire out
);

specify
    // Specparam declaration to define timing parameters
    specparam TRise = 5; // Rise time delay
    specparam TFall = 3; // Fall time delay

    // Path declarations to specify delays between signals
    (a => out) = (TRise, TFall);   // Delay from input 'a' to output 'out'
    (b => out) = (TRise, TFall);   // Delay from input 'b' to output 'out'
endspecify

// Logic for the output
assign out = a & b; // Example combinational logic

endmodule

The assign statement describes what the cell computes, and the specify block describes when the output changes. If b is 1 and a rises at time 10, out rises at time 15; if a then falls at time 30, out falls at time 33.

As with gate delays, a path delay can be one value for all transitions, two values for rise and fall, or three values for rise, fall and turn-off. Each value can also be a min:typ:max triple.

Synthesis result: None. Synthesis tools ignore specify blocks, because the timing of the synthesized circuit comes from the target library. Specify blocks belong in simulation models of cells, not in RTL that will be synthesized.

Module Paths

A module path connects a source, which must be an input or inout port, to a destination, which must be an output or inout port with only one driver inside the module. Paths can be simple, edge-sensitive or state-dependent.

Simple Module Paths

There are two ways to connect the source to the destination:

• Full connection *>: every bit of every source connects to every bit of every destination. Several sources and destinations can be listed, separated by commas.
• Parallel connection =>: bit 0 of the source connects to bit 0 of the destination, bit 1 to bit 1, and so on. Source and destination must have the same width.

specify
    // Full connection using the (*>) operator
    (c, a *> z) = 5;  // Delay of 5 time units for a simple path from 'a' to 'z' or 'c' to 'z'

    // Parallel connection using the (=>) operator
    (b => y) = 10;  // Delay of 10 time units from input 'b' to output 'y'
endspecify

For 2-bit ports in[1:0] and out[1:0], the two connections describe different sets of paths:

Use => when each output bit depends only on the matching input bit, as in a buffer or inverter bank, and *> when any input bit can affect any output bit, as in an adder or a decoder.

Edge Sensitive Paths

An edge-sensitive path applies only when a particular edge occurs on the source, such as the clock of a flip-flop. The destination is followed by a colon and the data source, the input whose value is passed to the output:

specify
    // Edge-sensitive path declaration
    (posedge clk => (data_out : data_in)) = 5;  // Delay of 5 time units for the rising edge of 'clk' affecting 'data_out'
endspecify

This reads as "on a rising edge of clk, data_out takes the value of data_in after 5 time units", which is the clock-to-output delay of a flip-flop. Without an edge keyword, the path applies to any transition of the source. Many simulators also accept the shorter form (posedge clk *> data_out) = 5; without the data source, but the form with ( : ) is the one defined by the standard.

State Dependent Paths

A state-dependent path applies its delay only while a condition is true. This models cells whose delay depends on the value of another input, for example a mux whose delay from one input differs depending on the select.

specify
    // State-dependent path declaration
    if (a) (enable => data_out) = 10;  // Delay of 10 time units when 'a' is true
    if (reset ==0) (enable => data_out) = 5; // Delay of 5 time units when 'reset' is low
endspecify

The condition can only use ports and constants of the module. If several conditions are true at the same time, the simulator uses the smallest of their delays.

ifnone Condition

ifnone gives the delay to use when none of the conditions of the state-dependent paths is true. It must have exactly the same source and destination as those paths.

specify
    // Default state-dependent path delay using ifnone
    ifnone (enable => data_out) = (15.0, 15.0);           // Default delay of 15 time units when no other conditions are met
endspecify

Together with the two conditional paths above, the delay from enable to data_out is 10 while a is 1, 5 while reset is 0, the smaller value 5 when both are true, and 15 otherwise. ifnone cannot be combined with an unconditional path between the same two ports, because the unconditional path would already cover every case.

Timing Checks

Besides delays, a specify block can check that the inputs of a cell follow its timing rules. The most common checks are for the setup and hold times of a flip-flop: the data must be stable for a minimum time before the clock edge (setup) and after it (hold). The flip-flop model below uses the d_flop primitive from Verilog UDP:

module dff_cell (input clk, d, output q);

  d_flop u0 (q, clk, d);           // Functional model of the flip-flop

  specify
    specparam tCQ = 3;             // Clock to output delay
    specparam tSU = 2;             // Setup time
    specparam tHD = 1;             // Hold time

    (posedge clk => (q : d)) = tCQ;

    $setup (d, posedge clk, tSU);  // d must be stable 2 units before the edge
    $hold  (posedge clk, d, tHD);  // and 1 unit after it
  endspecify

endmodule

If d changes 1 time unit before a rising edge of clk, the setup check is violated, and the simulator prints a warning with the time and the names of the signals. The simulation continues; the check only reports the problem. In library models, an extra notifier argument, such as $setup(d, posedge clk, tSU, notifier);, toggles a register on every violation, and the cell's UDP uses it to set q to x, just as a real flip-flop could go metastable.

Common Beginner Mistakes

module mux2_cell (input a, b, sel, output y);

  assign y = sel ? b : a;

  specify
    specparam tD_RISE = 2;
    specparam tD_FALL = 3;
    specparam tSEL    = 4;

    (a, b *> y) = (tD_RISE, tD_FALL);   // Data inputs to output
    (sel => y)  = tSEL;                 // Select to output
  endspecify

endmodule