A T flip-flop (toggle flip-flop) inverts its output on every active clock edge while its t input is 1, and holds its output while t is 0. In Verilog, you write it as a clocked always block that assigns q <= ~q when t is high.
10 min read | Beginner Level
What You'll Learn
- How a T flip-flop toggles and holds, and its characteristic equation
- Write a T flip-flop with a synchronous reset in Verilog
- What synthesis builds from it, since standard cell libraries have no T flip-flop cell
- Use T flip-flops for divide-by-2 and counter logic, and verify one with a testbench
What is a T Flip-Flop?
A T flip-flop has a clock (clk), a toggle input (t) and an output (q). The design in this article also has an active-low synchronous reset (rstn). At each rising edge of clk:
- t = 0: q holds its current value.
- t = 1: q toggles to the opposite value.
| rstn | t | q (current) | q (next) | Behavior |
|---|---|---|---|---|
| 0 | x | x | 0 | Reset |
| 1 | 0 | 0 | 0 | Hold |
| 1 | 0 | 1 | 1 | Hold |
| 1 | 1 | 0 | 1 | Toggle |
| 1 | 1 | 1 | 0 | Toggle |
The table reduces to the characteristic equation of a T flip-flop:
q(next) = t ^ q
When t is held at 1, the output toggles on every rising edge, so q is a square wave at half the clock frequency. This divide-by-2 behavior is the main reason T flip-flops appear in counters and clock dividers.
Syntax
Basic Form:
always @(posedge clk)
if (!rstn) // Reset first
q <= 0;
else if (t) // Toggle when t is 1
q <= ~q;
// No else needed: q holds its value when t is 0
Components:
posedge clk- Clock edge at whichqmay change (required)if (!rstn)- Reset to a known value; without it,qstays unknown in simulation (strongly recommended)q <= ~q- Toggle: the new value is the inverse of the current value (required)
Variations:
// 1. Asynchronous reset: add the reset edge to the sensitivity list
always @(posedge clk or negedge rstn)
if (!rstn) q <= 0;
else if (t) q <= ~q;
// 2. Equation form: same hardware, written from the characteristic equation
always @(posedge clk)
if (!rstn) q <= 0;
else q <= t ^ q;
// 3. Always toggle (divide-by-2): t is effectively tied to 1
always @(posedge clk)
if (!rstn) q <= 0;
else q <= ~q;
Design
module tff (
input clk, // Clock
input rstn, // Active-low synchronous reset
input t, // Toggle enable: 1 = toggle, 0 = hold
output reg q // Flip-flop output
);
always @(posedge clk) begin
if (!rstn) // Reset sampled at the clock edge
q <= 0; // Gives q a known starting value
else if (t)
q <= ~q; // Toggle: next value is the inverse of the current one
else
q <= q; // Hold; optional, since an unassigned reg in a
// clocked block keeps its value anyway
end
endmodule
Synthesis result: Standard cell libraries and FPGA fabrics have no dedicated T flip-flop cell. Synthesis builds one from a D flip-flop plus an XOR gate that computes t ^ q and feeds it back to the D input. Because the reset here is synchronous, it adds gating in front of D as well, so the D input is rstn & (t ^ q). On an FPGA, this logic fits in one LUT feeding the slice's flip-flop.
The XOR feedback is the toggle. When t is 1, the XOR passes the inverse of q to D, and when t is 0, it passes q unchanged. See D Flip-Flop Async Reset for how the flip-flop and its reset styles work.
Quick Check
Q: q is 0 and t is held at 1 for four rising clock edges. What is q after each edge?
Show Answer
1, 0, 1, 0. The output toggles on every edge, so it completes one full period every two clock edges, which is half the clock frequency.
Using a T Flip-Flop as a Divide-by-2
Tie t to 1 and the T flip-flop becomes a frequency divider. Each output period spans two clock periods.
// q toggles on every rising edge of clk, so clk_div2 runs at clk/2
tff u_div2 (
.clk (clk),
.rstn (rstn),
.t (1'b1), // Always toggle
.q (clk_div2)
);
Use a divided signal as a clock with care.
Driving other flip-flops from clk_div2 creates a new clock domain that static timing analysis must treat as a generated clock. In FPGA designs especially, the usual practice is to keep one clock and use the T flip-flop output as an enable that is high every other cycle.
Where is a T Flip-Flop Used?
Binary counters are the main use. In a synchronous counter, bit i toggles when all lower bits are 1, which is exactly T flip-flop behavior with t = q[i-1] & ... & q[0]. Event counters, timers and program counters in processors all use this toggle structure, usually written as count <= count + 1. See 4-bit counter for the vector form.
Ripple Counters and Clock Dividers
Chaining T flip-flops so that each output clocks the next produces a ripple counter. Each stage halves the frequency, so N stages divide by 2N. Low-power designs use this to derive slow timer ticks from a crystal oscillator, for example dividing 32.768 kHz by 215 to get a 1 Hz tick for a real-time clock. See Verilog Ripple Counter.
Testbench
The testbench generates a 10 ns clock, holds reset for the first two rising edges, then drives a new random value onto t every dly time units, 20 times. dly is chosen once with $random and reused for every step. See Verilog Testbench for testbench structure.
module tb;
reg clk;
reg rstn;
reg t;
reg [4:0] dly; // Delay between t changes, picked once (0 to 31)
integer i;
wire q;
tff u0 ( .clk (clk),
.rstn (rstn),
.t (t),
.q (q));
// Clock: period of 10, rising edges at 5, 15, 25, ...
always #5 clk = ~clk;
initial begin
dly = $random; // One random delay, reused for every step
{rstn, clk, t} <= 0; // Start in reset with t = 0
$monitor ("T=%0t rstn=%0b t=%0d q=%0d", $time, rstn, t, q);
// Hold reset for two rising edges, then release it
repeat(2) @(posedge clk);
rstn <= 1;
// Drive a random t every dly time units
for (i = 0; i < 20; i = i + 1)
#(dly) t <= $random; // t is 1 bit, so it takes bit 0
#20 $finish;
end
endmodule
ncsim> run T=0 rstn=0 t=0 q=x T=5 rstn=0 t=0 q=0 T=15 rstn=1 t=0 q=0 T=19 rstn=1 t=1 q=0 T=25 rstn=1 t=1 q=1 T=35 rstn=1 t=1 q=0 T=43 rstn=1 t=0 q=0 T=47 rstn=1 t=1 q=0 T=55 rstn=1 t=0 q=1 T=59 rstn=1 t=1 q=1 T=65 rstn=1 t=1 q=0 T=67 rstn=1 t=0 q=0 T=71 rstn=1 t=1 q=0 T=75 rstn=1 t=0 q=1 T=79 rstn=1 t=1 q=1 T=83 rstn=1 t=0 q=1 T=87 rstn=1 t=1 q=1 T=95 rstn=1 t=0 q=0 Simulation complete via $finish(1) at time 115 NS + 0
Reading the log against the rising edges at 5, 15, 25, and so on:
- Reset: q is x at time 0 and becomes 0 at the first rising edge (5), because reset is a synchronous input sampled at the edge.
- Toggle: t is 1 at the edges at 25 and 35, so q goes 0 to 1, then back to 0.
- Hold: t is 0 at the edge at 45 and at 85, so q keeps its value.
- Same-time change: At 55, t changes to 0 in the same time step as the rising edge, but q still toggles. The testbench drives t with a non-blocking assignment, so the flip-flop samples the old value of t (1) at the edge. The same happens at 75.
Common Beginner Mistakes
Mistake #1: Leaving out the reset
Wrong: always @(posedge clk) if (t) q <= ~q;
Right: always @(posedge clk) if (!rstn) q <= 0; else if (t) q <= ~q;
Why? A reg starts as x in simulation, and ~x is still x, so q stays unknown forever no matter how many times it toggles. A D flip-flop recovers as soon as it captures a known d, but a T flip-flop only ever inverts its own value, so it needs a reset to start from a known state.
Mistake #2: Writing the toggle in a combinational block
Wrong: always @(*) if (t) q = ~q;
Right: always @(posedge clk) if (t) q <= ~q;
Why? Without a clock edge, the block re-triggers every time q changes, and each run changes q again. The simulator hangs in a zero-delay loop, and synthesis builds a combinational loop (an inverter feeding itself) that oscillates instead of storing a value.
Mistake #3: Using t as the clock
Wrong: always @(posedge t) q <= ~q;
Right: always @(posedge clk) if (t) q <= ~q;
Why? With posedge t, synthesis uses t as the flip-flop's clock. The output then changes at a time set by the logic driving t, not by the system clock, which creates a new clock domain and timing problems. Keep clk as the clock and use t as an enable.
Mistake #4: Holding t high for more than one cycle when you want a single toggle
Wrong: Connecting a button or status signal that stays high for many cycles directly to t
Right: Convert the signal into a one-cycle pulse first, using an edge detector
Why? The flip-flop toggles on every clock edge where t is 1. A signal that is high for 1000 cycles produces 1000 toggles, and the final value depends on whether that count is odd or even. See Verilog Positive Edge Detector for generating a single-cycle pulse.
Practice Exercise
Challenge: 2-bit Synchronous Counter from T Flip-Flops
Build a module count2 with inputs clk and rstn and a 2-bit output count. Instantiate the tff module twice, with no other always blocks. After reset, count should go 0, 1, 2, 3, 0, ... on successive rising edges.
Hint
Bit 0 toggles on every edge. Bit 1 toggles only when bit 0 is 1. Both flip-flops share the same clock.
Solution
module count2 (
input clk,
input rstn,
output [1:0] count
);
// Bit 0: t tied to 1, so it toggles on every rising edge
tff u_bit0 (.clk(clk), .rstn(rstn), .t(1'b1), .q(count[0]));
// Bit 1: toggles only when bit 0 is 1, which is when bit 0 is about to wrap
tff u_bit1 (.clk(clk), .rstn(rstn), .t(count[0]), .q(count[1]));
endmodule
From count = 2'b01, both t inputs are 1 at the next edge, so both bits toggle and the counter moves to 2'b10. For a 3-bit counter, bit 2 would use t = count[1] & count[0]. This is the same logic that synthesis builds from count <= count + 1.
Summary
In this tutorial, you learned:
- A T flip-flop toggles
qat the clock edge whentis 1 and holds it whentis 0 - Its characteristic equation is
q(next) = t ^ q - Synthesis builds it from a D flip-flop with an XOR gate on its input, since there is no T flip-flop cell
- A reset is required, because toggling an unknown value keeps it unknown
- With
ttied to 1, the output runs at half the clock frequency - Chained T flip-flops form binary counters, where each bit toggles when all lower bits are 1
- Keep
clkas the clock and treattas an enable, using a one-cycle pulse when a single toggle is wanted
