Sequential Logic with always

Common Error:

Testbench

First declare all variables used in the testbench and start a clock using a simple always block that can be driven to the design. Then instantiate the design and connect its ports with corresponding testbench variables. Note that q is of type wire because it is connected to an output of the design which will be actively driving it. All other inputs to the design are of type reg so that they can be driven within a procedural block such as initial.

The stimulus first initializes all inputs to the design to zero and then de-asserts reset after some time. A for loop is used to drive different values to j and k which are driven at random times. Once the loop is done, wait for some more time and finish the simulation.

module tb;
	// Declare testbench variables
	reg j, k, rstn, clk;
	wire q; 				// Output from DUT (must be wire)
	integer i;
	reg [2:0] dly;

	// Generate clock: 50% duty cycle, 20ns period (50 MHz)
	always #10 clk = ~clk;

	// Instantiate the JK flip-flop design under test
	jk_ff u0 (
		.j(j),
		.k(k),
		.clk(clk),
		.rstn(rstn),
		.q(q)
	);

	// Stimulus generation
	initial begin
		// Initialize all inputs to zero at time 0
		{j, k, rstn, clk} <= 0;

		// Release reset after 10ns to start operation
		#10 rstn <= 1;

		// Apply random stimulus: 10 iterations
		for (i = 0; i < 10; i = i+1) begin
			dly = $random; // Random delay (0-7 ns)
			#(dly) j <= $random; // Random J input
			#(dly) k <= $random; // Random K input
		end

		// Let simulation run a bit longer, then finish
		#20 $finish;
	end

	// Monitor output changes
	initial begin
		$monitor("Time=%0t | rstn=%b j=%b k=%b q=%b",
		$time, rstn, j, k, q);
	end

	// Waveform dumping for analysis
	initial begin
		$dumpfile("jk_ff.vcd");
		$dumpvars(0, tb);
	end
endmodule

Note from the simulation wave that at the posedge of clock, output q changes value based on the state of inputs j and k as given in the truth table.

Modulo-10 Counter

Modulus(MOD) counters simply count up to a certain number before rolling back to zero. A MOD-N counter will count from 0 to N-1 and then roll back to zero and start counting again. Such counters typically require ceil(log₂N) flops to hold the count value. Shown below is the Verilog code for a MOD-10 counter that keeps counting up at every clock clk as long as reset rstn is deasserted.

Verilog parameters can be used to make a MOD-N counter which is more scalable.

// Modulo-10 Counter: Counts from 0 to 9, then rolls over
module mod10_counter (
	input clk, // Clock input
	input rstn, // Synchronous active-low reset
	output reg [3:0] out // 4-bit output (0-9, needs 4 bits)
);

	// Sequential logic: triggered on rising clock edge only
	always @ (posedge clk) begin
		if (!rstn) begin
			// Synchronous reset: counter resets to 0 on next clock edge
			// (Unlike asynchronous reset, this waits for clock edge)
			out <= 0;
		end else begin
			// Counter logic
			if (out == 9) // Check if reached maximum count
				out <= 0; // Roll over to 0
			else
				out <= out + 1; // Increment counter
		end
	end
endmodule

Synchronous vs. Asynchronous Reset:

• Synchronous Reset: Sensitivity list is @(posedge clk) only. Reset takes effect on next clock edge. Easier to meet timing, better for most designs.
• Asynchronous Reset: Sensitivity list is @(posedge clk or negedge rstn). Reset takes effect immediately. Used when instant reset is critical (e.g., safety systems).

Testbench

The testbench first declares some variables that can be assigned some values and driven to the design inputs. The counter module is then instantiated and connected with the testbench signals which are later driven with some values in the stimulus. Since the counter also requires a clock, the testbench clock is modeled with an always block. The stimulus simply sets default values at time 0ns, then deasserts reset after 10ns and the design is allowed to run for some time.

module tb;
	reg clk, rstn;
	wire [3:0] out; // Counter output (wire, not reg)

	// Instantiate the modulo-10 counter
	mod10_counter u0 (
		.clk(clk),
		.rstn(rstn),
		.out(out)
	);

	// Generate clock: 20ns period
	always #10 clk = ~clk;

	// Stimulus
	initial begin
		// Initialize signals
		{clk, rstn} <= 0;

		// Release reset after 10ns
		#10 rstn <= 1;

		// Let counter run for multiple cycles to observe rollover
		#450 $finish;
	end

	// Display counter value at each change
	initial begin
		$monitor("Time=%0t | rstn=%b out=%0d", $time, rstn, out);
	end

	// Waveform dump
	initial begin
		$dumpfile("mod10_counter.vcd");
		$dumpvars(0, tb);
	end
endmodule

See that the counter module counts from zero to 9, rolls over to zero and starts counting again.

4-bit Left Shift Register

Shown below is a 4-bit left shift register that accepts an input d into LSB and all other bits will be shifted left by 1. For example, if d equals zero and the initial value of the register is 0011, it will become 0110 at the next edge of the clock clk.

// 4-bit Left Shift Register
module lshift_4b_reg (
 input d, // Serial data input (enters at LSB)
 input clk, // Clock signal
 input rstn, // Synchronous active-low reset
 output reg [3:0] out // 4-bit parallel output
);

 // Sequential logic: shift operation on clock edge
 always @ (posedge clk) begin
 if (!rstn) begin
 // Reset: clear all bits
 out <= 0;
 end else begin
 // Left shift operation:
 // - out[3] gets out[2] (MSB shifts out, lost)
 // - out[2] gets out[1]
 // - out[1] gets out[0]
 // - out[0] gets d (new bit enters at LSB)
 // Concatenation syntax: {out[2:0], d}
 out <= {out[2:0], d};
 end
 end
endmodule

Shift Register Applications:

• Serial-to-Parallel Conversion: UART, SPI, I2C interfaces use shift registers to receive serial data
• Delay Lines: FIR filters use shift registers to create tapped delay lines for signal processing
• Pattern Detection: Communication systems shift in bits to detect sync patterns (e.g., Ethernet preamble)
• CRC Calculation: Linear Feedback Shift Registers (LFSRs) implement CRC error detection

FPGA Optimization: On Xilinx and Intel FPGAs, shift registers are recognized by the synthesizer and mapped to specialized SRL (Shift Register LUT) primitives instead of discrete flip-flops. A 32-bit shift register might use 32 flip-flops normally, but with SRL inference, it uses just 1-2 LUTs--a 90%+ resource savings! Write your shift registers in the standard pattern shown here, and modern synthesis tools will automatically optimize them.

Testbench

The testbench follows a similar template like the one shown before where some variables are declared, design module is instantiated and connected with the testbench signals. Then a clock is started and the stimulus is driven to the design using an initial block. In this testbench example, different values of d has to be exercised and hence a for loop is used to iterate 20 times and apply random values to the design.

module tb;
 reg clk, rstn, d;
 wire [3:0] out;
 integer i;

 // Instantiate the 4-bit left shift register
 lshift_4b_reg u0 (
 .d(d),
 .clk(clk),
 .rstn(rstn),
 .out(out)
 );

 // Generate clock
 always #10 clk = ~clk;

 // Stimulus
 initial begin
 // Initialize all signals
 {clk, rstn, d} <= 0;

 // Release reset
 #10 rstn <= 1;

 // Shift in 20 random bits, synchronized to clock edge
 for (i = 0; i < 20; i=i+1) begin
 @(posedge clk) d <= $random; // Apply new bit at clock edge
 end

 // Wait a bit and finish
 #10 $finish;
 end

 // Monitor shift register value
 initial begin
 $monitor("Time=%0t | d=%b out=%b", $time, d, out);
 end

 // Waveform dump
 initial begin
 $dumpfile("lshift_4b.vcd");
 $dumpvars(0, tb);
 end
endmodule

Note that each bit is shifted to the left by 1 and the new value of d is applied to LSB.

Common Beginner Mistakes

always @(posedge clk) begin 
	q = d; 
end

always @(posedge clk) begin 
	q <= d; 
end

 
always @(posedge clk) 
	if (!rstn) q <= 0; 
	else q <= d;

 
always @(posedge clk or negedge rstn)

always @(posedge clk)

always @(posedge clk or a or b) begin 
	q <= a + b; 
end

always @(*) 
	sum = a + b;

always @(posedge clk) 
	q <= sum;

if (out == 10) 
	out <= 0;

if (out == 9) 
	out <= 0; 
else 
	out <= out + 1;

parameter N = 10;

// other code

if (out == N-1) 
	out <= 0; 
else 
	out <= out + 1;