Verilog Coding Style Effect

Verilog is a hardware description language: every line of RTL ends up as gates and flip-flops. A consistent, well-organized coding style keeps code readable, maintainable and free of errors, but it does more than that. The way a circuit is described also affects synthesis, the step that turns RTL into a gate-level netlist for an FPGA or ASIC. Two descriptions with exactly the same behavior can lead the synthesis tool to different structures, with different area, timing and power.

10 min read | Beginner Level

What You'll Learn

• How three equivalent ways to write the same counter lead to different logic in the synthesis schematic
• Why the RTL schematic and the final optimized netlist can differ
• How writing style influences resource sharing and priority logic
• How to write RTL that is both readable and efficient

The three examples below describe a 2-bit counter with a synchronous, active-low reset that counts 0, 1, 2, 3 and then returns to 0. Every counter needs an adder to increment the value and flip-flops to store it, so those parts are the same in all three. The only difference is how the condition that returns the counter to 0 is written, and therefore how the reset logic is built.

Example #1

The first version combines the reset and the wrap-around condition into one expression: the counter is cleared when rstn is 0 or when both bits of out are 1.

module cntr_mod3 (input clk, rstn, output reg [1:0] out);
  always @(posedge clk) begin
    if (!rstn | out[1] & out[0])
      out <= 0;
    else
      out <= out + 1;
  end
endmodule

The tool builds the logic exactly as described: an AND gate for out[1] & out[0], and an OR gate that combines it with the inverted reset. Note that & has a higher precedence than |, so the condition reads as !rstn | (out[1] & out[0]).

Example #2

The second version keeps the reset and the wrap-around in separate, nested if statements, and tests the wrap-around with a comparison against 3:

module cntr_mod3 (input clk, rstn, output reg [1:0] out);
  always @(posedge clk) begin
    if (!rstn)
      out <= 0;
    else
      if (out == 3)
        out <= 0;
      else
        out <= out + 1;
  end
endmodule

Each if becomes its own multiplexer, so the schematic has two multiplexers in a chain, along with the logic for the out == 3 comparison. Before optimization, this uses more gates than Example #1, and therefore more area and power.

Example #3

The third version keeps the nested structure, but tests the wrap-around with the reduction AND operator &out, which is 1 only when every bit of out is 1:

module cntr_mod3 (input clk, rstn, output reg [1:0] out);
  always @(posedge clk) begin
    if (!rstn)
      out <= 0;
    else
      if (&out)
        out <= 0;
      else
        out <= out + 1;
  end
endmodule

Synthesis produces a single multiplexer and a reduction AND element, matching the RTL description. Each of the three styles has its trade-offs: Example #1 is the most compact but mixes reset and function in one expression, while Examples #2 and #3 keep the reset separate, which is easier to read and to reuse with a different reset scheme.

RTL Schematic vs Optimized Netlist

The schematics above are the RTL view that synthesis tools show right after reading the code, before optimization. They mirror the code structure, which makes them useful to see how a coding style is interpreted. The final netlist, however, is produced after optimization, which removes redundant logic.

Because a 2-bit counter wraps from 3 to 0 by itself, an optimizing tool can recognize that the wrap-around condition never changes the result, and all three examples can end up as the same small netlist: two flip-flops with synchronous reset and the increment logic. The differences in the schematics are real, but for logic this simple, the optimizer usually removes them.

Coding style matters most where the tool cannot prove that two descriptions are equivalent, or where the description fixes a structure that the tool will keep, such as an expensive operator that is written twice.

Despite the module name cntr_mod3, these counters have four states, 0 to 3. A mod-3 counter, with the states 0, 1 and 2, must return to 0 when out == 2. See Verilog Mod-N Counter.

Synthesis result: Use the area and timing reports of the optimized netlist, not the RTL schematic, to compare coding styles. The RTL view shows how the tool understood the code; the reports show what it finally built.

Resource Sharing

A clearer case where style changes the result is resource sharing. Both lines below select between two sums, but they describe different hardware:

// Style A: two adders, then a multiplexer
assign y = sel ? (a + b) : (c + d);

// Style B: two multiplexers, then one adder
assign y = (sel ? a : c) + (sel ? b : d);

For 32-bit values, an adder is much larger than a multiplexer, so Style B is smaller. Style A, on the other hand, is faster: both sums are computed in parallel and only a multiplexer follows them, while in Style B the multiplexers delay the start of the addition. Many synthesis tools can share resources automatically, but only within limits, so writing the shared version directly is the reliable way to get it when area matters.

Common Beginner Mistakes

// Style 1: reset and wrap-around in one condition
module cntr_mod3_a (input clk, rstn, output reg [1:0] out);
  always @(posedge clk)
    if (!rstn | out[1] & ~out[0])
      out <= 0;
    else
      out <= out + 1;
endmodule

// Style 2: separate reset branch
module cntr_mod3_b (input clk, rstn, output reg [1:0] out);
  always @(posedge clk)
    if (!rstn)
      out <= 0;
    else if (out == 2)
      out <= 0;
    else
      out <= out + 1;
endmodule