Verilog D Flip-Flop

A D flip-flop with asynchronous reset captures its data input on the rising edge of the clock and clears its output the moment reset is asserted, without waiting for a clock edge. In Verilog, you write it with an always @(posedge clk or negedge rstn) block that checks reset first.

12 min read | Beginner Level

What You'll Learn

• How a D flip-flop captures data on a clock edge, and how asynchronous and synchronous resets differ
• Write both reset styles in Verilog
• What each style synthesizes into, and when to choose one over the other
• How to verify reset behavior with a testbench and avoid common reset coding errors

What is a D Flip-Flop?

A D flip-flop is an edge-triggered storage element. At each rising edge of clk, it copies its data input d to its output q. Between edges, q holds its value no matter how d changes. This is the key difference from a level-sensitive D latch, which follows its input for as long as its enable is high.

A reset input forces q to a known value, usually 0, so the design starts in a defined state. The designs in this article use an active-low reset, rstn, where 0 means "reset".

For correct capture, d must be stable for a short setup time before the clock edge and a hold time after it. Static timing analysis checks these requirements; see Verilog Timing Checks.

Syntax

Basic Form (asynchronous active-low reset):

always @(posedge clk or negedge rstn)   // Wake up on a clock edge OR on reset assertion
  if (!rstn)                            // Reset is checked first
    q <= 0;                             // Reset value
  else
    q <= d;                             // Normal operation: capture d

Components:

• posedge clk - The clock edge that captures data (required)
• negedge rstn - Makes the reset asynchronous; the edge must match the reset's active level, so an active-low reset uses negedge (required for async reset)
• if (!rstn) - Reset test, which must be the first statement in the block (required)
• <= - Non-blocking assignment, the standard for sequential logic (required)

Variations:

// 1. Synchronous reset: reset is not in the sensitivity list
always @(posedge clk)
  if (!rstn) q <= 0;
  else       q <= d;

// 2. Asynchronous active-high reset: posedge rst, test if (rst)
always @(posedge clk or posedge rst)
  if (rst) q <= 0;
  else     q <= d;

// 3. Multi-bit register: the same code, with vector ports
//    input [7:0] d; output reg [7:0] q;  ->  q <= 8'h00 on reset

Design #1: With async active-low reset

With an asynchronous reset, rstn is in the sensitivity list. The block runs when rstn falls, so q clears immediately, even if the clock is stopped.

module dff (
  input      d,       // Data input, captured on the rising clock edge
  input      rstn,    // Active-low asynchronous reset
  input      clk,     // Clock
  output reg q        // Registered output
);

  // Block runs on a rising clock edge OR when rstn falls (reset asserted)
  always @(posedge clk or negedge rstn)
    if (!rstn)        // Reset asserted: clear q immediately, no clock needed
      q <= 0;
    else              // Reached only on a rising clock edge with reset released
      q <= d;

endmodule

Synthesis result: The tool maps this block to a single D flip-flop cell with an asynchronous clear pin (often named CLR, CDN or RN). rstn connects straight to that pin, so the reset path does not pass through any logic in front of d. This pattern, an edge-triggered sensitivity list with the reset test first, is the template synthesis tools look for when inferring an async-reset flop.

Testbench

The testbench generates a clock with a period of 20 time units, holds reset at the start, then changes d after random delays. At the end, it asserts reset halfway between two clock edges for 10 time units. This shows the difference between the two reset styles. See Verilog Testbench for testbench structure.

module tb_dff;
  reg clk;
  reg d;
  reg rstn;
  reg [2:0] delay;      // Random delay between d changes (0 to 7)
  integer i;
  wire q;

  // Connect testbench signals to the design ports
  dff dff0 ( .d    (d),
             .rstn (rstn),
             .clk  (clk),
             .q    (q));

  // Clock: toggles every 10 time units, so rising edges at 10, 30, 50, ...
  always #10 clk = ~clk;

  initial begin
    $monitor ("[%0t] clk=%0b rstn=%0b d=%0b q=%0b", $time, clk, rstn, d, q);

    // 1. Start in reset
    clk  <= 0;
    d    <= 0;
    rstn <= 0;

    // 2. Change d while reset is held: q must stay 0
    #15 d <= 1;

    // 3. Release reset at t=25, between clock edges
    #10 rstn <= 1;

    // 4. Change d after random delays; d is 1 bit, so it takes bit 0 of i
    for (i = 0; i < 5; i = i + 1) begin
      delay = $random;
      #(delay) d <= i;
    end

    // 5. Assert reset 5 time units after a rising edge, hold it for 10,
    //    and release it 5 time units before the next rising edge
    @(posedge clk);
    #5  rstn <= 0;
    #10 rstn <= 1;

    #30 $finish;
  end
endmodule

When you run it, check these points in the output:

• q is 0 from time 0, and stays 0 at the rising edge at 10 and when d becomes 1 at 15, because reset is still held.
• After reset is released at 25, q changes only at rising edges (30, 50, ...), taking the value d had just before the edge.
• In step 5, q drops to 0 at the same time step that rstn falls, between clock edges.

Design #2: With sync active-low reset

With a synchronous reset, rstn is not in the sensitivity list. The block runs only on the clock edge, so reset is just another input that is sampled at the edge, like d.

module dff_sync (
  input      d,       // Data input
  input      rstn,    // Active-low synchronous reset
  input      clk,     // Clock
  output reg q
);

  // Block runs only on the rising clock edge; rstn is sampled like data
  always @(posedge clk)
    if (!rstn)        // Reset seen at a clock edge: clear q
      q <= 0;
    else
      q <= d;

endmodule

Synthesis result: The tool builds a plain D flip-flop with no reset pin, plus a small gate in front of its D input. Here the next value is rstn ? d : 0, which reduces to an AND gate: D = rstn & d. Some cell libraries provide flip-flops with a built-in synchronous reset input that absorbs this gate.

To test this design, use the same testbench and change the instance to dff_sync dff0 (...). Most of the output is the same, with two differences:

• q is unknown (x) until the first rising edge at 10 ns, because a synchronous reset has no effect without a clock edge.
• In step 5, reset is held from 5 ns after one rising edge until 5 ns before the next, so no rising edge ever sees rstn = 0. The reset is missed entirely and q never clears.

module reg4 (
  input            clk,
  input            rst,     // Active-high asynchronous reset
  input            en,      // Load enable
  input      [3:0] d,
  output reg [3:0] q
);

  always @(posedge clk or posedge rst)
    if (rst)                // Reset first: q is set to 4'hA immediately
      q <= 4'hA;
    else if (en)            // On a clock edge, load d only when enabled
      q <= d;
    // No final else: q holds its value when en = 0

endmodule