Verilog FSM

A finite state machine (FSM) is a sequential circuit that is always in one of a fixed number of states. On each clock edge, it moves to a next state chosen by its current state and its inputs, and it produces outputs based on its state, and sometimes its inputs. In Verilog, an FSM is usually written as a clocked always block that holds the state register and a combinational always block that computes the next state.

12 min read | Intermediate Level

What You'll Learn

• The difference between Moore and Mealy FSMs, and between binary and one-hot state encoding
• Write an FSM with the two-block style: a state register and next-state logic
• Generate outputs combinationally or from registers, and what each style synthesizes into
• Avoid latches, lost states and reset problems in FSM code

Types of FSMs

FSMs are classified in two independent ways: by how their outputs are produced, and by how their states are encoded in flip-flops.

By output generation:

By state encoding:

One-hot encoding is the same idea as a ring counter: each state has its own flip-flop. It is popular on FPGAs, which have many flip-flops, while ASIC designs with many states often use binary encoding to save area. Synthesis tools can also re-encode an FSM automatically when they recognize the structure.

Verilog FSM Structure

An FSM can be written with one always block or with two. The two-block style is recommended because it separates the two kinds of hardware in an FSM:

• A clocked (sequential) block that holds the current state in a register
• A combinational block that computes the next state from the current state and the inputs

Outputs are produced either inside the combinational block or with separate assign statements, or from registers when glitch-free outputs are needed.

The states are given names with localparam, so the code reads IDLE instead of 2'b00, and the encoding can be changed in one place. See Verilog Parameters.

// State encoding: binary, 2 bits for 3 states
localparam IDLE    = 2'b00,
           STATE_1 = 2'b01,
           STATE_2 = 2'b10;

reg [1:0] cur_state;     // Output of the state register
reg [1:0] next_state;    // Output of the next-state logic

Sequential Always Block

The state register changes only on the clock edge. On reset, the FSM goes back to IDLE; otherwise it loads the next state computed by the combinational block. This block uses only non-blocking assignments, which model the register correctly and avoid race conditions with other clocked blocks.

always @ (posedge clk) begin
  // If reset is asserted, go back to IDLE state
  if (! resetn) begin
    cur_state <= IDLE;

  // Else transition to the next state
  end else begin
    cur_state <= next_state;
  end
end

Combinational Always Block

This block computes the next state. It uses always @(*), so it re-evaluates whenever the current state or any input changes, and it uses blocking assignments, as all combinational blocks should. It starts with a default assignment so that every path assigns next_state.

// Combinational always block for next state logic
always @(*) begin
    // Default: stay in the current state unless a transition below applies
    next_state = cur_state;

    case (cur_state)
        IDLE: begin
                if (input_signal)
                  next_state = STATE_1; // Transition to STATE_1 on input_signal
              end

        STATE_1:  begin
                    if (!input_signal)
                      next_state = STATE_2; // Transition to STATE_2 if input_signal is low
                  end

        STATE_2:  next_state = IDLE; // Transition back to IDLE
        default:  next_state = IDLE; // Recover from any unused encoding (2'b11)
    endcase
end

The default next_state = cur_state means "stay here" for every case that does not name a transition. So the FSM waits in IDLE until input_signal goes high, and waits in STATE_1 until it goes low. The default item of the case handles 2'b11, the one encoding that is not a valid state, by returning to IDLE.

Output Generation

There are three common ways to produce the FSM's outputs.

1. In the combinational block. Assign a default value to every output at the start of the block, then override it in the states or transitions that need it. Assigning outputs in the same case as the next state keeps all the behavior of a state in one place. When several outputs change together, the assignments can be grouped in a task.

always @(*) begin
    next_state    = cur_state;
    output_signal = 1'b0;            // Default output value: no latch can be inferred

    case (cur_state)
        IDLE:     if (input_signal)
                    next_state = STATE_1;

        STATE_1:  if (!input_signal) begin
                    next_state    = STATE_2;
                    output_signal = 1'b1;    // Depends on state AND input: Mealy output
                  end

        STATE_2:  next_state = IDLE;
        default:  next_state = IDLE;
    endcase
end

Here output_signal is 1 during the cycle in which the FSM is in STATE_1 and input_signal is low. Because it depends on an input, it is a Mealy output.

2. With continuous assignments. A Moore output can be written as a comparison on the current state. This is clear for a few outputs, but becomes repetitive when there are many states and outputs.

assign  op_signal = (cur_state == STATE_1) ? 1 : 0;

3. From registers. Computing the output's next value combinationally and storing it in a flip-flop gives a glitch-free output that changes exactly on the clock edge, at the cost of one more flip-flop per output:

// Registered Moore output: high for exactly the cycles the FSM is in STATE_2
always @(posedge clk) begin
  if (!resetn) done <= 1'b0;
  else         done <= (next_state == STATE_2);
end

Using next_state rather than cur_state makes done line up with the state: it goes high on the same edge on which the FSM enters STATE_2.

Complete Example

Putting the pieces together gives a full module. Its single Moore output, busy, is high whenever the FSM is not in IDLE.

module simple_fsm (
  input      clk,
  input      resetn,        // Active-low synchronous reset
  input      input_signal,
  output     busy           // Moore output
);

  localparam IDLE    = 2'b00,
             STATE_1 = 2'b01,
             STATE_2 = 2'b10;

  reg [1:0] cur_state, next_state;

  // 1. State register
  always @(posedge clk) begin
    if (!resetn) cur_state <= IDLE;
    else         cur_state <= next_state;
  end

  // 2. Next-state logic
  always @(*) begin
    next_state = cur_state;
    case (cur_state)
      IDLE    : if (input_signal)  next_state = STATE_1;
      STATE_1 : if (!input_signal) next_state = STATE_2;
      STATE_2 : next_state = IDLE;
      default : next_state = IDLE;
    endcase
  end

  // 3. Output logic
  assign busy = (cur_state != IDLE);

endmodule

Synthesis result: The tool builds a 2-bit state register (two flip-flops with synchronous reset), a small block of combinational logic for the next state, made of the muxes and gates described by the case statement, and an OR gate for busy, which is 1 whenever either state bit is 1. Many synthesis tools recognize this structure as an FSM, report its states and transitions, and can choose a different encoding, such as one-hot, if it gives better timing.

Elaborated Schematic

In the elaborated view, the current-state register appears as flip-flops, and the next-state logic appears as multiplexers selected by the current state and the inputs. The two-block coding style maps directly onto three parts of hardware:

• Present-state logic: the clocked block, which becomes the state register
• Next-state logic: the combinational block, which becomes muxes and gates
• Output logic: the output assignments, which become gates driven by the state register (and the inputs, for Mealy outputs)

Keeping these parts separate in the code makes the FSM easier to read, review and change. See Verilog Pattern Detector for a complete FSM example with a testbench.

Common Beginner Mistakes

module traffic_light (
  input  clk,
  input  resetn,      // Active-low synchronous reset
  input  tick,        // Advance to the next light when 1
  output red,
  output yellow,
  output green
);

  localparam RED    = 2'd0,
             GREEN  = 2'd1,
             YELLOW = 2'd2;

  reg [1:0] cur_state, next_state;

  // State register
  always @(posedge clk) begin
    if (!resetn) cur_state <= RED;
    else         cur_state <= next_state;
  end

  // Next-state logic: advance only on tick
  always @(*) begin
    next_state = cur_state;               // Hold by default
    if (tick) begin
      case (cur_state)
        RED     : next_state = GREEN;
        GREEN   : next_state = YELLOW;
        YELLOW  : next_state = RED;
        default : next_state = RED;
      endcase
    end
  end

  // Moore outputs: depend only on the current state
  assign red    = (cur_state == RED);
  assign green  = (cur_state == GREEN);
  assign yellow = (cur_state == YELLOW);

endmodule