JK Flip Flop

A JK flip-flop is an edge-triggered storage element with two control inputs: j sets the output, k resets it, both low holds it, and both high toggles it. In Verilog, you write it as a clocked always block with a case statement on {j, k}.

10 min read | Beginner Level

What You'll Learn

• The four JK operations (hold, reset, set, toggle) and the characteristic equation
• Write a JK flip-flop in Verilog using a case statement
• What synthesis builds from it, and how JK relates to D, T and SR flip-flops
• Verify all four operations with a self-checking testbench

What is a JK Flip-Flop?

A JK flip-flop has a clock (clk), two inputs (j and k) and an output (q). At each rising edge of clk, the pair {j, k} selects one of four operations:

Writing the table as a sum of products gives the characteristic equation:

q(next) = (j & ~q) | (~k & q)

Read it as two cases. When q is 0, the next value is j. When q is 1, the next value is ~k. Between clock edges, q holds its value no matter how j and k change.

A JK flip-flop is an SR flip-flop with the forbidden state removed. On an SR flip-flop, S = R = 1 is invalid; on a JK flip-flop, j = k = 1 is defined as toggle. This makes JK a general-purpose element that can act as a D or T flip-flop with simple input wiring.

Syntax

Basic Form:

always @(posedge clk)
  case ({j, k})           // Concatenate j and k into a 2-bit selector
    2'b00 : q <= q;       // Hold
    2'b01 : q <= 1'b0;    // Reset
    2'b10 : q <= 1'b1;    // Set
    2'b11 : q <= ~q;      // Toggle
  endcase

Components:

• posedge clk - Clock edge at which q may change (required)
• {j, k} - Concatenation with j as the upper bit, so 2'b10 means j = 1, k = 0 (required); see Verilog Concatenation
• 2'b11 : q <= ~q - The toggle case that distinguishes JK from SR (required)

Variations:

// 1. Equation form: same hardware, written from the characteristic equation
always @(posedge clk)
  q <= (j & ~q) | (~k & q);

// 2. With active-low asynchronous reset
always @(posedge clk or negedge rstn)
  if (!rstn) q <= 1'b0;
  else
    case ({j, k})
      2'b01 : q <= 1'b0;
      2'b10 : q <= 1'b1;
      2'b11 : q <= ~q;
      default: ;           // 2'b00: hold, q keeps its value
    endcase

Design

The case statement maps directly to the truth table, which makes the code easy to check against the specification. See Verilog case statement for the statement itself.

module jk_ff (
  input      j,       // Set input
  input      k,       // Reset input
  input      clk,     // Clock
  output reg q        // Flip-flop output
);

  // Evaluate j and k only at the rising clock edge
  always @(posedge clk)
    case ({j, k})
      2'b00 : q <= q;      // Hold: keep the current value
      2'b01 : q <= 1'b0;   // Reset: force q to 0
      2'b10 : q <= 1'b1;   // Set: force q to 1
      2'b11 : q <= ~q;     // Toggle: invert the current value
    endcase

endmodule

Synthesis result: Modern standard cell libraries and FPGA fabrics have no JK flip-flop cell. Synthesis builds one from a D flip-flop with a small block of logic in front of its D input that implements the characteristic equation, D = (j & ~q) | (~k & q). The output q feeds back into that logic. On an FPGA, the three-input function (j, k, q) fits in a single LUT.

Hardware Schematic

JK as a Universal Flip-Flop

Because the JK flip-flop has all four operations, other flip-flop types can be built from it by wiring its inputs:

See Verilog T Flip Flop for the toggle-only version.

Testbench

This testbench is self-checking. It applies a sequence of {j, k} pairs that covers all four operations, and after each rising edge it compares q with a simple reference model. Inputs change on the falling edge, so they are stable well before the rising edge that samples them. See Verilog Testbench for testbench structure.

module tb_jk;
  reg        clk;
  reg        j, k;
  wire       q;
  reg        exp_q;               // Expected q from the reference model
  reg  [1:0] jk_seq [0:7];        // {j, k} pairs to apply, in order
  integer    i, errors;

  jk_ff u0 (.j(j), .k(k), .clk(clk), .q(q));

  // Clock: period of 10, rising edges at 5, 15, 25, ...
  always #5 clk = ~clk;

  initial begin
    // Stimulus sequence: start with reset, since q is x until set or reset
    jk_seq[0] = 2'b01;   // Reset:  q -> 0
    jk_seq[1] = 2'b00;   // Hold:   q stays 0
    jk_seq[2] = 2'b10;   // Set:    q -> 1
    jk_seq[3] = 2'b00;   // Hold:   q stays 1
    jk_seq[4] = 2'b11;   // Toggle: q -> 0
    jk_seq[5] = 2'b11;   // Toggle: q -> 1
    jk_seq[6] = 2'b01;   // Reset:  q -> 0
    jk_seq[7] = 2'b11;   // Toggle: q -> 1

    clk    = 0;          // Initialize clk, or ~x stays x and no edge ever occurs
    {j, k} = 2'b00;
    errors = 0;
    exp_q  = 1'bx;

    for (i = 0; i < 8; i = i + 1) begin
      @(negedge clk);             // Change inputs away from the rising edge
      {j, k} = jk_seq[i];

      @(posedge clk);             // Flip-flop samples j and k here
      #1;                         // Let q update before checking

      // Reference model, written as a lookup instead of the equation
      case ({j, k})
        2'b00 : exp_q = exp_q;
        2'b01 : exp_q = 1'b0;
        2'b10 : exp_q = 1'b1;
        2'b11 : exp_q = ~exp_q;
      endcase

      $display("[%0t] j=%b k=%b q=%b", $time, j, k, q);
      if (q !== exp_q) begin
        $display("  ERROR: expected q=%b", exp_q);
        errors = errors + 1;
      end
    end

    if (errors == 0) $display("PASS: all JK operations correct");
    else             $display("FAIL: %0d mismatches", errors);
    $finish;
  end
endmodule

Each line of output is printed 1 time unit after a rising edge: at 16, 26, 36, and so on. With a correct design, q follows the sequence 0, 0, 1, 1, 0, 1, 0, 1, and the run ends with a PASS line.

Common Beginner Mistakes

module jk_ff_rst (
  input      j,
  input      k,
  input      clk,
  input      rstn,    // Active-low asynchronous reset
  output reg q
);

  always @(posedge clk or negedge rstn)
    if (!rstn)                    // Reset first, without waiting for clk
      q <= 1'b0;
    else
      case ({j, k})
        2'b00 : q <= q;           // Hold
        2'b01 : q <= 1'b0;        // Reset
        2'b10 : q <= 1'b1;        // Set
        2'b11 : q <= ~q;          // Toggle
      endcase

endmodule