Before learning Verilog syntax, it helps to understand where Verilog fits in the design of a chip. A modern chip contains billions of transistors, far too many for anyone to think about one at a time. Engineers manage this complexity with abstraction: they describe the design at different levels of detail, and each level hides the details of the levels below it. Verilog is mainly used at one of these levels, the register transfer level (RTL).
10 min read | Beginner Level
What You'll Learn
- The five abstraction layers of chip design: architecture, RTL, schematic, transistor and physical
- The difference between top-down and bottom-up design methods
- How abstraction is used to organize a design and divide the work
- Which abstraction level to use for a task, and why RTL code should stay at its own level
Real-World Application
In a system-on-chip (SoC) project, the architecture, RTL, synthesis and physical design teams all work at the same time, each at its own abstraction layer. Architects define the blocks and their interfaces, RTL designers write and verify the Verilog for each block, synthesis engineers turn it into gates, and physical designers place and route those gates on silicon. This division of labor is what allows hundreds of engineers to build a chip with billions of transistors.
Design Abstraction
Abstraction layers are different levels of detail for describing the same hardware. They let a designer focus on one aspect of the design, such as what a block does, without being overwhelmed by the details of how it is built underneath. Moving down the layers adds detail; moving up hides it.
Architecture Level
The architecture level is the highest layer. It divides the system into sub-blocks grouped by their function, and defines how they communicate. A processor cluster with its cores, caches and coherence logic is a single block at this level, described only by what it does and which signals and buses connect it to the rest of the chip.
At this level, decisions are about performance, power and cost: how many cores, how much cache, how wide the buses are. These decisions are usually explored with models written in a software language before any RTL exists.
RTL Level
At the register transfer level (RTL), each sub-block is described in a hardware description language such as Verilog. The description says how data moves between registers and which operations are applied to it on each clock cycle, but it does not say which gates or transistors are used, and it does not depend on a particular technology library. A large block, such as a memory controller, is usually spread over many Verilog files.
The 32-bit ALU below is a typical RTL description:
module alu_32b (a, b, operation, result);
input [31:0] a;
input [31:0] b;
input [1:0] operation;
output reg [31:0] result;
always @(a or b or operation) begin
case (operation)
2'b00: result = a & b; // AND
2'b01: result = a | b; // OR
2'b10: result = a + b; // Addition
2'b11: result = a - b; // Subtraction
endcase
end
endmodule
The ALU selects one of four operations, AND, OR, addition or subtraction, based on the 2-bit operation input. Nothing in the code says how the adder is built or how fast it is; those choices are left to synthesis.
Synthesis result: Synthesis turns this case statement into a 4:1 multiplexer of 32 bits, fed by 32 AND gates, 32 OR gates, a 32-bit adder and a 32-bit subtractor. A good tool often shares one adder for both + and -, because subtraction is addition of the inverted operand plus one. The case covers all four values of operation, so no latch is inferred.
Schematic Level
At the schematic or gate level, the design is described as gates and flip-flops connected by wires. Synthesis tools produce this level automatically from RTL, using a technology library that describes the cells available in a particular manufacturing process, such as AND gates, multiplexers and flip-flops, with their timing and power.
A small function can also be designed at this level by hand. A truth table lists every combination of inputs and the output for each one:
Boolean algebra and Karnaugh maps can turn a truth table into a gate schematic. This works well for small blocks, but it is impractical for something like a processor, with thousands of inputs and internal states. That is why designs are written in RTL and converted to gates by tools.
Transistor Level
At the transistor level, each gate is built from transistors. In CMOS technology, a NAND gate uses two PMOS transistors in parallel to connect the output to the supply Vdd, and two NMOS transistors in series to connect it to ground. Design decisions here include the width of each transistor's channel, the supply voltage, and how much capacitive load the gate must be able to drive.
Most digital designers never work at this level. The cells of the technology library are designed once by circuit designers, and then reused in every design. See Verilog Switch Level Modeling for how transistors can be modeled in Verilog.
Physical Level
At the physical level, the transistors and wires are drawn as shapes on the different layers of the silicon: diffusion, polysilicon and several metal layers. This layout is what is sent for fabrication. Designing it requires knowledge of the devices and the manufacturing technology, because the size and position of every shape affect the resistance, capacitance and reliability of the circuit.
For the digital part of a chip, the layout is created mostly by place-and-route tools, which place the library cells and connect them with metal wires according to the gate-level netlist.
Quick Check
At which abstraction level does a designer decide that an adder should be 32 bits wide, and at which level is it decided which kind of adder circuit is used?
Show Answer
The width is part of the RTL description, such as input [31:0] a. The kind of adder circuit, such as ripple-carry or a faster structure, is chosen at the gate level, normally by the synthesis tool based on the timing constraints.
Design Styles
Digital design mainly uses two methods to move between these levels: top-down and bottom-up.
Top-Down
Top-down design starts with the top-level block and its requirements. The designer identifies the sub-modules needed to build it, then breaks each sub-module into smaller sub-blocks, and continues until reaching leaf cells that cannot be divided further. Specifications flow from the top of the hierarchy to the bottom.
Bottom-up
Bottom-up design starts with the building blocks that are available. Small cells are designed and characterized first, then connected to build larger cells, which are combined again until the top-level block is complete.
Real projects use both methods at the same time. Architects define the system, and designers implement the blocks in RTL and synthesize them: that is top-down. The gates that synthesis maps to, however, were created bottom-up: circuit designers built and optimized each standard cell as a transistor layout, and characterized its timing and power for the library. Synthesis tools then instantiate those standard cells. The two flows meet at the gate level.
For RTL designers, this means: describe the function correctly and clearly in RTL, and leave the gate-level optimization to synthesis. Hand-written gate-level code usually gives worse quality of results (QoR) in area, timing and power than the same function written in RTL and optimized by the tool.
Quick Check
A team designs a new standard cell library and then uses it to build a processor. Which part of this is top-down and which is bottom-up?
Show Answer
Designing the cells from transistors and then characterizing them is bottom-up. Defining the processor architecture, splitting it into blocks, writing RTL and synthesizing it onto the cells is top-down.
Common Beginner Mistakes
Mistake #1: Writing gate primitives instead of RTL
Wrong:
// WRONG - Structurally instantiating individual gates at RTL
and a1 (n1, a, b);
and a2 (n2, c, d);
or o1 (out, n1, n2);
Right:
// CORRECT - Behavioral description; synthesis picks the gates
assign out = (a & b) | (c & d);
// Synthesis will find optimal gate structure
Why? Wiring gate primitives by hand fixes a structure before synthesis, which gives the tool less freedom to optimize and makes the code harder to read. A Boolean assign describes the same function and lets synthesis choose the best cells, for example a single AND-OR cell.
Mistake #2: Mixing abstraction levels in one module
Wrong:
// WRONG - RTL module instantiating transistor-level primitives
module controller (input clk, rst_n, output reg state);
wire drain, source, gate;
nmos n1 (drain, source, gate); // Transistor primitive in RTL!
// ... RTL logic
endmodule
Right:
// CORRECT - Pure RTL description
module controller (input clk, rst_n, input next_state, output reg state);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
state <= 1'b0;
else
state <= next_state; // RTL behavior only
end
endmodule
Why? Transistor primitives cannot be synthesized, and they make the module dependent on one technology, harder to verify and impossible to optimize. Keep each module within one abstraction level.
Mistake #3: Ignoring timing in RTL
Wrong:
// WRONG - Combinational path too long, no pipeline consideration
always @(*) begin
result = ((a * b) + (c * d)) / ((e * f) - (g * h)); // Huge combinational delay!
end
Right:
// CORRECT - Pipelined for better timing
always @(posedge clk) begin
// Stage 1: Multiply
mult_ab <= a * b;
mult_cd <= c * d;
mult_ef <= e * f;
mult_gh <= g * h;
// Stage 2: Add/Subtract
sum <= mult_ab + mult_cd;
diff <= mult_ef - mult_gh;
// Stage 3: Divide
result <= sum / diff;
end
Why? RTL does not specify gates, but it does decide how much logic sits between two registers. A long chain of multipliers, an adder and a divider in one clock cycle limits the maximum clock frequency. Splitting the work into pipeline stages with registers in between shortens each path, at the cost of a few cycles of latency. The divider in stage 3 is still large and slow; in a real design it would be replaced by a multi-cycle divider.
Mistake #4: Using expensive operators without thinking about hardware
Wrong:
// WRONG - Division by variable synthesizes to expensive hardware
always @(*) begin
quotient = dividend / divisor; // Variable divisor = complex divider circuit!
end
Right:
// CORRECT - Division by constant power-of-2 = simple shift
assign quotient = dividend >> 4; // Divide by 16, synthesizes to wires
// Or for variable division, use multi-cycle sequential divider
// (implementation omitted for brevity)
Why? RTL lets you write / as easily as +, but the hardware is very different: a divider by a variable is a large, slow circuit, while division by a power of two is just a shift, which costs no gates at all. Thinking one level down, about what synthesis will build, is part of writing good RTL.
Practice Exercise
Challenge: Identify Abstraction Levels and Design Flow
A chip project produces these six items:
- A block diagram showing a CPU, memory and I/O connected by a bus
- Verilog code of a 32-bit ALU
- The truth table of a NAND gate
- A CMOS schematic of a NAND gate with four transistors
- A polygon layout of a NAND gate
- SystemVerilog code of a cache controller state machine
Classify each item by abstraction level, put them in the order of a design flow, identify who or what creates each level, and state how each level is verified.
Hint
Ask how much detail each item contains. A block diagram shows only blocks and connections; HDL code describes behavior; a truth table or gate schematic describes logic; a transistor schematic shows devices; a layout shows shapes on silicon.
Solution
| Element | Abstraction Level | Explanation |
|---|---|---|
| 1. CPU/Memory/I/O block diagram | Architecture Level | Shows system-level organization without implementation details |
| 2. Verilog ALU code | RTL Level | Behavioral hardware description using HDL |
| 6. SystemVerilog cache controller | RTL Level | Behavioral description with state machines |
| 3. NAND gate truth table | Schematic/Gate Level | Defines logic function of a gate |
| 4. CMOS transistor schematic | Transistor Level | Shows circuit implementation using transistors |
| 5. Polygon layout | Physical Level | Actual silicon layout for fabrication |
Design flow: top-down, the flow runs from the architecture (1) to RTL (2 and 6) and then to gates. Bottom-up, the NAND cell is designed as transistors (4), laid out (5), and characterized so that it can be described by its function (3) in the gate library. Synthesis of the RTL (top-down) uses those standard cells (bottom-up), so the two flows meet at the gate level.
| Level | Designer-Created | Tool-Generated |
|---|---|---|
| Architecture | Block diagrams, specifications | |
| RTL | Verilog/SystemVerilog code | |
| Gate | Synthesis tools create netlists | |
| Transistor | Standard cell design (library creation) | |
| Physical | Some manual floorplanning | Place-and-route tools |
Verification: RTL is verified with simulation testbenches and assertions. The gate level is checked with gate-level simulation and equivalence checking against the RTL, and its timing with static timing analysis. Transistor-level cells are verified with circuit simulation (SPICE). The physical layout is checked with design rule checks (DRC), layout versus schematic (LVS) and parasitic extraction. Most functional bugs are found and fixed at the RTL level, where they are cheapest to fix.
Summary
In this tutorial, you learned:
- Chip design uses five abstraction layers: architecture, RTL, schematic or gate, transistor and physical
- Each layer describes the same hardware with a different level of detail, and tools translate one layer into the next
- Verilog RTL describes behavior between registers, and synthesis turns it into gates from a technology library
- Top-down design splits a system into smaller blocks; bottom-up design builds larger blocks from existing cells, and real projects use both
- Writing RTL at its own level, without gate or transistor primitives, keeps code portable, verifiable and easy to optimize
