Verilog Conditional Statements

Verilog conditional statements select which value is assigned, or which statements run, based on a condition. Verilog has three of them: the conditional operator ? :, the if-else statement and the case statement. In synthesizable RTL, each one describes selection hardware, usually a multiplexer.

12 min read | Beginner Level

What You'll Learn

• The syntax of the conditional operator, if-else and case, and where each can be used
• What hardware each construct synthesizes into
• How to choose the right construct for a given piece of logic
• How x values, multi-bit conditions and missing branches affect the result

Quick Reference

All three constructs choose between alternatives. They differ in where you can write them and how many alternatives they handle well.

// Conditional operator: inside a continuous assignment
assign y = sel ? a : b;

// if-else: inside a procedural block
always @(*)
  if (sel) y = a;
  else     y = b;

// case: inside a procedural block
always @(*)
  case (sel)
    1'b1    : y = a;
    default : y = b;
  endcase

These three blocks all describe the same 2 to 1 mux. In the last two, y must be declared as reg because it is assigned in an always block.

Conditional Operator

The conditional operator ? :, also called the ternary operator, picks one of two expressions based on a condition. It is an expression, not a statement, so it can appear anywhere a value is expected, including the right-hand side of an assign statement.

<variable> = <condition> ? <expression_1> : <expression_2>;

• <condition> - Evaluated first. Any non-zero value counts as true (required)
• <expression_1> - Result when the condition is true (required)
• <expression_2> - Result when the condition is false (required)

module max2 (
  input  [7:0] a,
  input  [7:0] b,
  output [7:0] max     // Driven by assign, so it stays a wire
);

  // If a is greater than b, output a; otherwise output b
  assign max = (a > b) ? a : b;

endmodule

Synthesis result: Each ? : becomes a 2 to 1 mux. Its select line comes from the condition logic, here an 8-bit magnitude comparator for a > b.

Nested conditional operators

The second or third operand can itself be a conditional expression, which lets one assignment choose between more than two values.

// "y" is assigned to "out" when both "a < b" and "x % 2" are true
// "z" is assigned to "out" when "a < b" is true and "x % 2" is false
// 0 is assigned to "out" when "a < b" is false
assign out = (a < b) ?  (x % 2) ? y : z : 0;

The operator groups from right to left, so the line above is read as (a < b) ? ((x % 2) ? y : z) : 0. Adding those inner parentheses yourself makes the intent clear to the next reader. Here, x % 2 is the remainder after dividing by 2, which is just the least significant bit of x, so synthesis needs no divider.

Synthesis result: Each nesting level adds one 2 to 1 mux to the path, forming a mux tree. The 4 to 1 multiplexer is the standard example: three conditional operators in a two-level tree.

Advantages:

• Concise: a full selection fits in a single line
• Works in continuous assignments, where if-else and case are not allowed
• Easy to read for simple two-way choices

Disadvantages:

• Each operator chooses between only two values
• Readability drops quickly beyond two levels of nesting
• Each expression can assign only one signal; selecting several signals needs one operator per signal

If a conditional expression needs more than two levels of nesting, rewrite it as a case statement inside an always @(*) block. The hardware is the same, and the code is much easier to review.

if-else statement

The if-else statement runs one group of statements when its condition is true and another when it is false. Unlike the conditional operator, it is a procedural statement, so it can only appear inside an always or initial block, and each branch can assign several signals. For chains of conditions, see Read more on Verilog if-else-if statements.

if (<condition>) begin
	// statement 1
end else begin
	// statement 2
end

• <condition> - Any expression; non-zero is true, zero is false (required)
• begin ... end - Groups several statements into one branch; optional when a branch has a single statement
• else - Runs when the condition is false (optional, but see the latch warning below)

module abs_diff (
  input      [7:0] a,
  input      [7:0] b,
  output reg [7:0] diff,     // |a - b|
  output reg       a_bigger  // 1 when a > b
);

  // Both outputs are assigned in every branch, so this is pure combinational logic
  always @(*) begin
    if (a > b) begin
      diff     = a - b;
      a_bigger = 1'b1;
    end else begin
      diff     = b - a;
      a_bigger = 1'b0;
    end
  end

endmodule

Synthesis result: A single if-else becomes one 2 to 1 mux per assigned signal, all controlled by the condition. Here the tool builds a comparator for a > b, two subtractors, and a mux that selects which difference reaches diff. a_bigger reduces to the comparator output itself. A chain of else if branches describes a priority chain, which keeps its ordering only when the conditions can be true at the same time; see Verilog Priority Encoder.

case (<expression>)
   value1: statement1;
   value2: statement2;
   ...
   default: statementN;
endcase

module seg_decoder (
  input      [1:0] digit,    // Value to display: 0 to 3
  output reg [6:0] seg       // Segments g..a of a 7-segment display, 1 = on
);

  always @(*) begin
    case (digit)
      2'd0    : seg = 7'b011_1111;   // Segments a-f on
      2'd1    : seg = 7'b000_0110;   // Segments b, c on
      2'd2    : seg = 7'b101_1011;   // Segments a, b, d, e, g on
      2'd3    : seg = 7'b100_1111;   // Segments a, b, c, d, g on
      default : seg = 7'b000_0000;   // All off; also covers x or z on digit
    endcase
  end

endmodule

module alu4 (
  input      [3:0] a,
  input      [3:0] b,
  input      [1:0] op,       // Operation select
  output reg [3:0] result,
  output           zero      // 1 when result is 0
);

  // case: one item per operation, so this builds a parallel 4 to 1 mux
  always @(*) begin
    case (op)
      2'b00   : result = a + b;   // Add (carry out is dropped)
      2'b01   : result = a - b;   // Subtract
      2'b10   : result = a & b;   // Bitwise AND
      2'b11   : result = a | b;   // Bitwise OR
      default : result = 4'b0;    // Covers x or z on op; prevents a latch
    endcase
  end

  // Conditional operator in a continuous assignment
  assign zero = (result == 4'b0) ? 1'b1 : 1'b0;

endmodule