Verilog Assignments

Race Condition Warning: If the variable is initialized during declaration and at time 0 in an initial block, the order of evaluation is not guaranteed, and the variable can have either value.

module my_block;
  reg [7:0] addr = 8'h05;    // Initialize to 0x05

  initial
    addr = 8'hee;            // Also assigns at time 0 - RACE CONDITION!
                             // Final value could be 0x05 OR 0xEE (undefined)
endmodule

Declaration Assignment Rules

reg [3:0] array [3:0] = 0;           // ILLEGAL - cannot initialize arrays
integer i = 0, j;                    // Declares two integers i, j; only i is assigned 0
real r2 = 4.5, r3 = 8.0;             // Declares r2=4.5, r3=8.0
time startTime = 40;                 // Declares time variable with initial value 40

Continuous Assignment

This is used to assign values onto scalar and vector nets (not variables) and happens whenever there is a change in the RHS. It provides a way to model combinational logic without specifying an interconnection of gates and makes it easier to drive the net with logical expressions.

Syntax

// Continuous assignment to a net
assign net_name = expression;

// Net declaration assignment (combined)
wire net_name = expression;

Example

// Example model of an AND gate
wire a, b, c;

assign a = b & c;            // Continuous assignment: a updates whenever b or c changes

Whenever b or c changes its value, then the whole expression in RHS will be evaluated and a will be updated with the new value immediately (in zero simulation time).

Net Declaration Assignment

This allows us to place a continuous assignment on the same statement that declares the net. Note that because a net can be declared only once, only one declaration assignment is possible for a net.

wire penable = 1;            // Declare wire and continuously assign it to 1

// is equivalent to

wire penable;
assign penable = 1;

Continuous Assignment Use Case: Use continuous assignments to model combinational logic, data path connections, and simple logic gates. The assignment is active throughout simulation--any change to the RHS immediately propagates to the LHS.

Procedural Continuous Assignment

These are procedural statements that allow expressions to be continuously assigned to nets or variables, overriding all other assignments. Note that the "nets or variables" flexibility applies to force/release only -- assign/deassign, despite the similar name, can only target variables (regs), never nets. They are primarily used in testbenches for debugging and forcing specific signal values. There are two types:

• assign ... deassign
• force ... release

assign / deassign

This will override all procedural assignments to a variable and is deactivated by using the same signal with deassign. The value of the variable will remain the same until the variable gets a new value through a procedural or procedural continuous assignment.

Restrictions: The LHS of an assign statement cannot be a bit-select, part-select or an array reference but can be a variable or a concatenation of variables.

Syntax

assign variable = expression;    // Override all procedural assignments to variable
deassign variable;               // Stop overriding (variable retains last assigned value)

Example

reg q;

initial begin
  assign q = 0;                  // Force q to 0 (overrides any other assignment)
  #10 deassign q;                // After 10 time units, stop forcing
                                 // q retains value 0 until next assignment
end

force / release

These are similar to the assign - deassign statements but can also be applied to nets (not just variables). The LHS can be a bit-select of a net, part-select of a net, variable or a net but cannot be the reference to an array and bit/part select of a variable.

The force statement will override all other assignments made to the variable or net until it is released using the release keyword.

Syntax

force net_or_variable = expression;    // Override all assignments (works on nets and variables)
release net_or_variable;               // Stop overriding

Example

reg o, a, b;

initial begin
  force o = a & b;               // Force o to be a&b (overrides any assignment to o)
  #50;                           // Hold for 50 time units
  release o;                     // Release the force (o resumes normal behavior)
end

Assignment Types Comparison

Common Beginner Mistakes

// WRONG - mixing assignment types with wrong target types
reg data;
wire addr;

assign data = 8'hAB;       // ERROR: Can't use assign on reg
always @(*) addr = input;  // ERROR: Can't use procedural assignment on wire

// CORRECT - proper assignment types
wire data;
reg addr;

assign data = 8'hAB;       // OK: assign to wire
always @(*) addr = input;  // OK: procedural assignment to reg

// WRONG - race condition between declaration and initial block
module race_example;
  reg [7:0] counter = 8'h00;   // Initialized at time 0

  initial begin
    counter = 8'hFF;             // Also executes at time 0 - RACE!
  end
endmodule

// CORRECT - single initialization source
module no_race;
  reg [7:0] counter;           // No declaration initialization

  initial begin
    counter = 8'hFF;             // Only initialization, no race
  end
endmodule

// WRONG - using procedural continuous in RTL
module bad_design (input clk, output reg q);
  always @(posedge clk) begin
    if (error_condition)
      assign q = 1'b0;       // ERROR: assign/deassign not synthesizable!
    else
      deassign q;
  end
endmodule

// CORRECT - synthesizable RTL
module good_design (input clk, output reg q);
  always @(posedge clk) begin
    if (error_condition)
      q <= 1'b0;             // OK: normal procedural assignment
    else
      q <= normal_value;
  end
endmodule

// WRONG - misunderstanding continuous assignment behavior
wire enable;
wire output_signal;

assign enable = 1'b1;              // Always drives enable to 1
assign output_signal = data & enable;   // Always evaluates

// Later, trying to disable:
always @(posedge clk) begin
  if (disable_condition)
    enable = 1'b0;                 // ERROR: Can't assign to wire from procedural block!
end

// CORRECT - condition in continuous assignment
wire enable;
wire output_signal;

assign enable = !disable_condition;     // Condition in continuous assignment
assign output_signal = data & enable;

// OR use reg with procedural assignment
reg enable;
always @(*) begin
  if (disable_condition)
    enable = 1'b0;
  else
    enable = 1'b1;
end