Gate Level Modeling

Most digital designs are written at a higher level of abstraction, such as RTL, but some small and deterministic circuits are easier to describe gate by gate, using elements such as AND and OR. Gate level modeling describes a circuit as a set of connected logic gates, so the Verilog code maps one to one onto the circuit's schematic.

12 min read | Beginner Level

What You'll Learn

• The built-in Verilog gate primitives and their port order
• Use multi-input gates, multi-output buffers and inverters, and tri-state gates
• Build a small circuit, a 2 to 1 mux, entirely from primitives
• How gate-level code relates to synthesized netlists, and common primitive mistakes

Gate Primitives

Verilog provides predefined gate primitives that are instantiated like modules, but without having to be declared. More complex behavior can be described with User Defined Primitives (UDPs).

Rules for instantiating primitives:

• The instance name, such as u0, is optional for primitives, unlike for modules.
• Connections are always by position. Primitives have no port names, so .a(x) style connections are not allowed.
• Outputs must connect to nets (wire), not to reg variables, because a primitive drives its output continuously.
• An optional delay can follow the gate type, such as and #2 u0 (out, a, b);. See Verilog Gate Delay.

And/Or/Xor Gates

The and, or and xor primitives take any number of scalar inputs and drive a single scalar output. The first terminal in the list is always the output, and it updates whenever any of the inputs changes.

module gates (	input a, b,
				output c, d, e);

	and (c, a, b); 	// c is the output, a and b are inputs
	or  (d, a, b);	// d is the output, a and b are inputs
	xor (e, a, b); 	// e is the output, a and b are inputs
endmodule

module tb;
	reg a, b;
	wire c, d, e;
	integer i;

	gates u0 ( .a(a), .b(b), .c(c), .d(d), .e(e));

	initial begin
		{a, b} = 0;

      $monitor ("[T=%0t a=%0b b=%0b c(and)=%0b d(or)=%0b e(xor)=%0b", $time, a, b, c, d, e);

		for (i = 0; i < 10; i = i+1) begin
			#1 	a <= $random;
				b <= $random;
		end
	end
endmodule

$ /usr/bin/vvp simulation +random_seed+1492585514
[T=0 a=0 b=0 c(and)=0 d(or)=0 e(xor)=0
[T=1 a=0 b=1 c(and)=0 d(or)=1 e(xor)=1
[T=2 a=1 b=1 c(and)=1 d(or)=1 e(xor)=0
[T=4 a=1 b=0 c(and)=0 d(or)=1 e(xor)=1
[T=5 a=1 b=1 c(and)=1 d(or)=1 e(xor)=0
[T=6 a=0 b=1 c(and)=0 d(or)=1 e(xor)=1
[T=7 a=1 b=0 c(and)=0 d(or)=1 e(xor)=1
[T=10 a=1 b=1 c(and)=1 d(or)=1 e(xor)=0

Each line matches the truth tables: c is 1 only when both inputs are 1, d when at least one is 1, and e when they differ. $monitor prints only when a value changes, so time steps where the random inputs repeat, such as T=3, do not appear.

Nand/Nor/Xnor Gates

The inverted versions, nand, nor and xnor, use the same syntax. The design below is the previous example with each primitive replaced by its inverted form.

module gates (	input a, b,
				output c, d, e);

	// Use nand, nor, xnor instead of and, or and xor
	// in this example
	nand (c, a, b); 	// c is the output, a and b are inputs
	nor  (d, a, b);		// d is the output, a and b are inputs
	xnor (e, a, b); 	// e is the output, a and b are inputs
endmodule

module tb;
	reg a, b;
	wire c, d, e;
	integer i;

	gates u0 ( .a(a), .b(b), .c(c), .d(d), .e(e));

	initial begin
		{a, b} = 0;

      $monitor ("[T=%0t a=%0b b=%0b c(nand)=%0b d(nor)=%0b e(xnor)=%0b", $time, a, b, c, d, e);

		for (i = 0; i < 10; i = i+1) begin
			#1 	a <= $random;
				b <= $random;
		end
	end
endmodule

$ /usr/bin/vvp simulation +random_seed+622900489
[T=0 a=0 b=0 c(nand)=1 d(nor)=1 e(xnor)=1
[T=1 a=0 b=1 c(nand)=1 d(nor)=0 e(xnor)=0
[T=2 a=1 b=1 c(nand)=0 d(nor)=0 e(xnor)=1
[T=4 a=1 b=0 c(nand)=1 d(nor)=0 e(xnor)=0
[T=5 a=1 b=1 c(nand)=0 d(nor)=0 e(xnor)=1
[T=6 a=0 b=1 c(nand)=1 d(nor)=0 e(xnor)=0
[T=7 a=1 b=0 c(nand)=1 d(nor)=0 e(xnor)=0
[T=10 a=1 b=1 c(nand)=0 d(nor)=0 e(xnor)=1

The input sequence is the same as before, and every output is now the inverse of the corresponding output in the previous log.

Like their non-inverted versions, these gates accept more than two inputs. The next example uses four-input and, or and nor gates.

module gates (	input a, b, c, d,
				output x, y, z);

  and (x, a, b, c, d); 	// x is the output, a, b, c, d are inputs
  or  (y, a, b, c, d);	// y is the output, a, b, c, d are inputs
  nor (z, a, b, c, d); 	// z is the output, a, b, c, d are inputs
endmodule

module tb;
	reg a, b, c, d;
	wire x, y, z;
	integer i;

  gates u0 ( .a(a), .b(b), .c(c), .d(d), .x(x), .y(y), .z(z));

	initial begin
      {a, b, c, d} = 0;

      $monitor ("[T=%0t a=%0b b=%0b c=%0b d=%0b x=%0b y=%0b z=%0b", $time, a, b, c, d, x, y, z);

		for (i = 0; i < 10; i = i+1) begin
			#1 	a <= $random;
				b <= $random;
          		c <= $random;
          		d <= $random;

		end
	end
endmodule

$ /usr/bin/vvp simulation +random_seed+1394207508
[T=0 a=0 b=0 c=0 d=0 x=0 y=0 z=1
[T=1 a=0 b=1 c=1 d=1 x=0 y=1 z=0
[T=2 a=1 b=1 c=1 d=0 x=0 y=1 z=0
[T=3 a=1 b=1 c=0 d=1 x=0 y=1 z=0
[T=4 a=1 b=0 c=1 d=0 x=0 y=1 z=0
[T=5 a=1 b=0 c=1 d=1 x=0 y=1 z=0
[T=6 a=0 b=1 c=0 d=0 x=0 y=1 z=0
[T=7 a=0 b=1 c=0 d=1 x=0 y=1 z=0
[T=8 a=1 b=1 c=1 d=0 x=0 y=1 z=0
[T=9 a=0 b=0 c=0 d=1 x=0 y=1 z=0
[T=10 a=0 b=1 c=1 d=1 x=0 y=1 z=0

The last value on each line is the nor output z. It is 1 only at T=0, when all four inputs are 0. The 4-input and output x stays 0 because all four inputs are never 1 at the same time in this run.

Buf/Not Gates

The buf and not primitives have a single scalar input and one or more outputs. A buffer passes its input to the output unchanged, and an inverter outputs the opposite value. In hardware, buffers are used to strengthen a signal so it can drive long wires or many loads.

module gates (	input a,
				output c, d);

  buf (c, a); 		// c is the output, a is input
  not (d, a);		// d is the output, a is input
endmodule

module tb;
	reg a;
	wire c, d;
	integer i;

	gates u0 ( .a(a), .c(c), .d(d));

	initial begin
		a = 0;

      $monitor ("[T=%0t a=%0b c(buf)=%0b d(not)=%0b", $time, a, c, d);

		for (i = 0; i < 10; i = i+1) begin
			#1 	a <= $random;
		end
	end
endmodule

$ /usr/bin/vvp simulation +random_seed+1384864616
[T=0 a=0 c(buf)=0 d(not)=1
[T=2 a=1 c(buf)=1 d(not)=0
[T=8 a=0 c(buf)=0 d(not)=1
[T=9 a=1 c(buf)=1 d(not)=0

For buf and not, the order of terminals is the opposite of the other gates: the last terminal is the input, and all terminals before it are outputs. This allows one gate to drive several outputs, although this form is rarely used.

module gates (	input  a,
				output c, d);

  not (c, d, a); 		// c,d is the output, a is input

endmodule

xcelium> run
[T=0 a=0 c=1 d=1
[T=2 a=1 c=0 d=0
[T=8 a=0 c=1 d=1
[T=9 a=1 c=0 d=0
xmsim: *W,RNQUIE: Simulation is complete.

Both c and d always hold the inverse of a.

Bufif/Notif

The bufif and notif primitives are a buffer and an inverter with an extra control input. They have a valid output only when the control signal is active; otherwise their output is high impedance (z), which means the gate is disconnected from the wire.

• bufif1 and notif1 drive their output when control is 1.
• bufif0 and notif0 drive their output when control is 0.

Because a disabled gate drives z, several tri-state gates can share one wire, as long as only one of them is enabled at a time. This is how a shared bus works. In the example below, sel enables exactly one of two buffers, which makes a 2 to 1 multiplexer:

module mux2_tri (input a, b, sel, output y);

  bufif0 u0 (y, a, sel);    // Drives y with a when sel = 0
  bufif1 u1 (y, b, sel);    // Drives y with b when sel = 1

endmodule

Both gates drive the same net y. For each value of sel, one of them drives the value and the other drives z, so the net resolves to the driven value. If sel is x, both gates may drive, and y becomes x wherever a and b differ.

Building a Circuit with Primitives

Larger circuits are built by connecting primitives with internal wires, exactly as in a schematic. A 2 to 1 multiplexer computes out = (a & ~sel) | (b & sel), which takes one inverter, two AND gates and one OR gate:

module mux2_gate (input a, b, sel, output out);

  wire sel_n, a_sel, b_sel;      // Internal connections between gates

  not u0 (sel_n, sel);           // sel_n = ~sel
  and u1 (a_sel, a, sel_n);      // a passes when sel = 0
  and u2 (b_sel, b, sel);        // b passes when sel = 1
  or  u3 (out, a_sel, b_sel);    // Combine the two paths

endmodule

Each line of code corresponds to one gate in the schematic, and each wire to one connection. Compare this with the same mux written in one line, assign out = sel ? b : a;, in Verilog 4 to 1 Multiplexer: the RTL version is shorter and leaves the choice of gates to the synthesis tool.

Synthesis result: Synthesis tools accept gate primitives and map each one to an equivalent cell of the target library, or, on an FPGA, merge them into LUTs. The tool may still optimize the logic, so the final netlist does not always contain one cell per primitive. If an exact structure must be kept, such as in a clock gating or synchronizer cell, engineers instantiate the specific library cells directly and mark them so the tool does not change them.

Common Beginner Mistakes

module full_adder_gate (input a, b, cin, output sum, cout);

  wire ab_x, ab_a, c_and;

  xor u0 (ab_x, a, b);           // a ^ b
  xor u1 (sum, ab_x, cin);       // sum = a ^ b ^ cin
  and u2 (ab_a, a, b);           // Carry generated by a and b
  and u3 (c_and, ab_x, cin);     // Carry propagated from cin
  or  u4 (cout, ab_a, c_and);    // cout

endmodule