Verilog if-else-if

  1. Syntax
  2. Hardware Implementation
    1. if without else
    2. if with else
    3. if else if
  3. Examples
    1. if without else for single statement
    2. if without else for multiple statements
    3. if-else for single statement
    4. if-else for multiple statements

This conditional statement is used to make a decision on whether the statements within the if block should be executed or not.

  • If the expression evaluates to true (i.e. any non-zero value), all statements within that particular if block will be executed
  • If it evaluates to false (zero or 'x' or 'z'), the statements inside if block will not be executed
  • If there is an else statement and expression is false then statements within the else block will be executed.

Syntax

If multiple statements need to be placed inside the if or else part, it needs to be enclosed within begin and end.


	if ([expression])
		Single statement

	// Use "begin" and "end" blocks for more than 1 statements		
	if ([expression]) begin          
		Multiple statements
	end
	
	// Use else to execute statements for which expression is false
	if ([expression]) begin
		Multiple statements
	end else begin
		Multiple statements
	end
	
	// if-else-if style to check for more expressions if the previous one doesn't match
	if ([expression 1]) 
		Single statement
	else if ([expression 2]) begin
		Multiple Statements
	end else
		Single statement

Hardware Implementation

if without else

if without an else part implies that the value remain unchanged for any condition that does not satisfy the expression inside if.


module des (  input en,
              input d,
              output reg q);

    always @ (en or d)
        if (en)
            q = d;

endmodule

Value of output q is updated whenever d or en changes in value.

if with else

Output q will get the value of input d at the positive edge of clock if rstn is high and describes the behavior of a D flop.


module dff (	input clk,
							input rstn,
							input d,
							output reg q);
							
	always @ (posedge clk) begin
		if (! rstn)
			q <= 0;
		else
			q <= d;
	end
endmodule

Note that the synthesized output indicates a flop with an output q .

if else if

In the following example, the design module has a 4-bit output q that is incremented when mode is 1 and decrements when mode is 2 with if else construct. Note that the description does not specify what has to be done if mode is 0 or 3 which are valid values for a 2-bit variable. It is assumed that the circuit does nothing when mode is 1 and 3, but maintain exiting value of q . It is not recommended to leave such ambiguity in real design code, but is shown here to highlight the possibility.


module des ( input [1:0] mode,
             input clk,
            input rstn,
            output reg [3:0] q);

  always @ (posedge clk) begin
    if (! rstn)
      q <= 0;
    else begin
      if (mode == 1)
        q <= q + 1;
      else if (mode == 2)
        q <= q - 1;
    end
  end
endmodule

The synthesized output may differ with availability of cells for a given technology library

Shown below is the synthesized output and it is worth to note that q got implemented as a 4-bit flop which has a pin CE to enable the flop. Note that this flop is enabled only when mode is 1 or 2 and not for other values. Output q is fed back through an adder and subtractor block into the input of the same flop through a mux which is again controlled by mode .

Consider the same design from above with a 1-bit mode .


module des ( input mode,
             input clk,
            input rstn,
            output reg [3:0] q);

  always @ (posedge clk) begin
    if (! rstn)
      q <= 0;
    else begin
      if (mode)
        q <= q + 1;
      else 
        q <= q - 1;
    end
  end
    
endmodule

In this case, a regular flop without a CE pin is used along with a few multiplexers to choose the correct signal based on value of mode .

Examples

if without else for single statement


module tb;
  int a = 10;
  
  initial begin 
    if (a == 10)      // if block can have only one statement in it
      $display ("a is found to be 10");
    $display ("Always executed regardless of value of a");   // This statement is outside if block because 
  end
endmodule
 Simulation Log
ncsim> run
a is found to be 10
Always executed regardless of value of a
ncsim: *W,RNQUIE: Simulation is complete.

if without else for multiple statements


module tb;
  int a = 10;
  
  initial begin
    if (a == 10) begin       // if block has begin end keywords, and can support multiple statements
       $display ("a is found to be 10");
       $display ("Its good to get 10");
       
       // Anything else can be done here until the "end" keyword
    end
    $display ("Always executed regardless of value of a");   // Statement is outside the if block, because of the closing "end" for the "begin" in if
  end
endmodule
 Simulation Log
ncsim> run
a is found to be 10
Its good to get 10
Always executed regardless of value of a
ncsim: *W,RNQUIE: Simulation is complete.

if-else for single statement


module tb;
  int a = 9;
 
  initial begin
    if (a == 10)
       $display ("a is found to be 10");    // Is executed when "if" expression is True
    else
       $display ("a is NOT 10 :(");         // Is executed when "if" expression is false
  end
endmodule
 Simulation Log
ncsim> run
a is NOT 10 :(
ncsim: *W,RNQUIE: Simulation is complete.

if-else for multiple statements


module tb;
  int a = 9;
 
  initial begin
    if (a == 10) begin
       $display ("a is found to be 10");              // Is executed when "if" expression is True
       // Can have more additional statements here
       
    end else begin
       $display ("a is NOT 10 :(");                   // Is executed when "if" expression is false
       $display ("Why is a not 10 ?");
       // Can have more additional statements here
    end
  end
endmodule
 Simulation Log
ncsim> run
a is NOT 10 :(
Why is a not 10 ?
ncsim: *W,RNQUIE: Simulation is complete.