A ripple counter is an asynchronous counter built from a chain of flip-flops in which only the first flip-flop is driven by the system clock. Every other flip-flop is clocked by the output of the one before it, so a change "ripples" through the chain one stage at a time. This article builds a 4-bit ripple counter in Verilog from D flip-flops.
10 min read | Beginner Level
What You'll Learn
- How a ripple counter divides the clock by 2 at each stage
- Build a 4-bit ripple counter from D flip-flops wired as toggle stages
- Why the clock edge and output choice decide between counting up and down
- How ripple delay causes glitches, and when to use a synchronous counter instead
How a Ripple Counter Works
Each stage is a D flip-flop with its inverted output qn fed back to its d input. At every active clock edge, the flip-flop captures the inverse of its current value, so it toggles. A flip-flop that toggles on every rising edge produces a square wave at half its clock frequency, which makes each stage a divide-by-2 circuit. This is the same behavior as a T flip-flop with its input tied to 1.
The first stage is clocked by clk, and each later stage is clocked by the q output of the stage before it. Stage 0 runs at clk/2, stage 1 at clk/4, stage 2 at clk/8 and stage 3 at clk/16. Together, the four outputs step through all 16 values of a 4-bit count.
The direction of the count depends on which edge clocks the next stage and which output is used:
- Stage i toggles when the
qof stage i-1 rises from 0 to 1. In a binary down count, that is exactly when a bit must flip, because a bit borrows from the next bit when it goes from 0 to 1. So theqoutputs count down. - The
qnoutputs are the inverse ofq, so they count up. This is why the design below usesqnfor its output.
Design
The design has two modules: a D flip-flop with asynchronous active-low reset and an inverted output, and the 4-bit counter that chains four of them.
module dff ( input d,
input clk,
input rstn,
output reg q,
output qn);
always @ (posedge clk or negedge rstn)
if (!rstn)
q <= 0;
else
q <= d;
assign qn = ~q; // Inverted output, used both for feedback and as the count
endmodule
module ripple ( input clk,
input rstn,
output [3:0] out);
wire q0;
wire qn0;
wire q1;
wire qn1;
wire q2;
wire qn2;
wire q3;
wire qn3;
// Stage 0: clocked by the system clock, toggles on every rising edge
dff dff0 ( .d (qn0),
.clk (clk),
.rstn (rstn),
.q (q0),
.qn (qn0));
// Stage 1: clocked by q0, toggles when q0 rises
dff dff1 ( .d (qn1),
.clk (q0),
.rstn (rstn),
.q (q1),
.qn (qn1));
// Stage 2: clocked by q1
dff dff2 ( .d (qn2),
.clk (q1),
.rstn (rstn),
.q (q2),
.qn (qn2));
// Stage 3: clocked by q2
dff dff3 ( .d (qn3),
.clk (q2),
.rstn (rstn),
.q (q3),
.qn (qn3));
// The q outputs count down, so their inverses count up
assign out = {qn3, qn2, qn1, qn0};
endmodule
Because the output is taken from qn, it is 4'hF while reset is active, not 0. On the first rising edge of clk after reset, every q toggles from 0 to 1 in turn, and out becomes 4'h0. From there it counts up: 1, 2, 3, and so on to F, then wraps to 0.
| Rising edges of clk after reset | q3 q2 q1 q0 | out = {qn3, qn2, qn1, qn0} |
|---|---|---|
| 0 (in reset) | 0000 | 1111 (F) |
| 1 | 1111 | 0000 (0) |
| 2 | 1110 | 0001 (1) |
| 3 | 1101 | 0010 (2) |
| 4 | 1100 | 0011 (3) |
Synthesis result: The tool builds exactly the structure written: four flip-flops, each with an inverter from q back to d, and the q of each stage connected to the clock pin of the next. No adder or incrementer is needed, which makes the ripple counter very small. Timing analysis, however, must treat q0, q1 and q2 as three additional generated clocks, and FPGA tools usually warn about logic-generated clocks.
Quick Check
Q: If the output is changed to assign out = {q3, q2, q1, q0};, what sequence does the counter produce after reset?
Show Answer
0, F, E, D, C and so on down to 0, repeating. The q outputs start at 0 in reset and count down, because each stage toggles when the previous q rises.
Hardware Schematic
In the schematic, only the first flip-flop's clock pin connects to clk. Each of the others is clocked by the output of its neighbor, which is the defining feature of a ripple counter.
Ripple Delay and Glitches
In real hardware, each flip-flop needs a short time after its clock edge before its output changes, called the clock-to-q delay (tcq). In a ripple counter, stage 1 cannot start changing until stage 0 has changed, stage 2 waits for stage 1, and so on. In the worst case, the last stage changes 4 x tcq after the clock edge in a 4-bit counter, and N x tcq in an N-bit counter.
While the change ripples through, the output passes through intermediate values. On the step from 7 to 8, for example, the q outputs change one at a time, so out briefly shows 6, 4 and 0 before settling at 8. Any logic that decodes the count, such as a comparator looking for the value 4, can see these short false values as glitches.
The design above has no delays, so in simulation all four stages change in the same simulation time step and the intermediate values do not appear in the waveform. To see the ripple, add a small delay to the flip-flop, such as q <= #1 d;, and look at out after each clock edge.
Ripple vs Synchronous Counter
| Ripple counter | Synchronous counter | |
|---|---|---|
| Clocking | Only the first stage uses the system clock | All flip-flops share the system clock |
| Logic | One inverter per stage | Incrementer in front of the flip-flops |
| Output settles | N x tcq after the edge, one bit at a time | tcq after the edge, all bits together |
| Glitches on decoded outputs | Yes, during the ripple | Much smaller, only from logic delay differences |
| Power | Low: later stages switch less often | Higher: every flip-flop is clocked on every edge |
| Use in modern RTL | Clock dividers and low-power timers | Almost all counting logic |
See 4-bit counter for the synchronous version, written as out <= out + 1.
Where are Ripple Counters Used?
Battery-powered devices often need a slow tick, such as a once-per-second timer, while the main clock is stopped. A ripple divider clocked by a low-frequency crystal oscillator produces it with very little power, because each later stage switches only half as often as the one before it, and only the first stage runs at the oscillator frequency.
Prescalers in Frequency Counters
Instruments that measure high-frequency signals first divide the input down with a prescaler, often a short ripple divider, because only its first stage has to run at the full input frequency. The slower divided signal is then counted by synchronous logic.
Testbench
The testbench generates a 10 ns clock, holds reset for four clock edges, then lets the counter run for 25 edges. A $monitor statement prints each change of out.
module tb_ripple;
reg clk;
reg rstn;
wire [3:0] out;
ripple r0 ( .clk (clk),
.rstn (rstn),
.out (out));
always #5 clk = ~clk; // 10 ns period
initial begin
$monitor ("[%0t] rstn=%0b out=0x%0h", $time, rstn, out);
rstn <= 0; // Assert reset: out = 4'hF
clk <= 0;
repeat (4) @ (posedge clk);
rstn <= 1; // Release reset
repeat (25) @ (posedge clk); // Count through more than one full cycle
$finish;
end
endmodule
The output should show out = F during reset, then 0 at the first rising edge after reset is released, counting up by one at each rising edge, wrapping from F to 0 and continuing until the simulation ends.
Quick Check
Q: Each flip-flop has a clock-to-q delay of 2 ns. In the worst case, how long after a rising edge of clk does the 4-bit output settle?
Show Answer
8 ns. On a step such as F to 0, all four stages toggle, and each one waits for the previous one, so the delays add up to 4 x 2 ns. A synchronous counter would settle about 2 ns after the edge, plus its output logic delay.
Discrete Counter Chips
Binary ripple counters were widely sold as single 74-series and 4000-series chips, with 4 to 14 stages in one package. They are still found in board-level designs as cheap clock dividers and long time-delay generators, and engineers meet them when converting older board designs into HDL.
Common Beginner Mistakes
Mistake #1: Taking the count from q and expecting it to count up
Wrong: assign out = {q3, q2, q1, q0}; with each stage clocked on the rising edge of the previous q
Right: Use {qn3, qn2, qn1, qn0}, or clock each stage from the previous qn instead
Why? A stage clocked by the rising edge of the previous q follows the rule of a down count. Either invert the outputs, as this design does, or clock each stage from the previous qn, which makes the q outputs count up.
Mistake #2: Decoding the ripple outputs directly
Wrong: assign hit = (out == 4'd4); used as an enable or a pulse for other logic
Right: Register the decoded value on a clock edge after the output has settled, or use a synchronous counter
Why? During the ripple, out passes through intermediate values, so hit can pulse briefly even when the count never truly equals 4. A short false pulse on an enable, a reset or a clock input causes unpredictable behavior.
Mistake #3: Sampling the ripple outputs with the main clock
Wrong: Feeding out straight into a register clocked by clk
Right: Treat the ripple outputs as a separate clock domain, or replace the counter with a synchronous one
Why? The higher bits change several clock-to-q delays after the clk edge, so a register clocked by clk may capture some bits before they change and others after. Timing analysis must model each stage as a generated clock to check this.
Mistake #4: Trusting zero-delay simulation for ripple timing
Wrong: Concluding from an RTL waveform that all bits change together
Right: Check ripple behavior with delays in the model, or with gate-level timing simulation
Why? Without delays, all stages update in the same simulation time step, which hides the ripple delay and the intermediate values that real hardware produces.
Practice Exercise
Challenge: Parameterized Ripple Counter with generate
Rewrite ripple as ripple_n with a parameter N for the number of stages. Use the dff module and a generate for loop, so that stage 0 is clocked by clk and stage i by the q of stage i-1. The output should count up.
Hint
Declare wire [N-1:0] q, qn;. Inside the loop, use a generate if (i == 0) to connect stage 0 to clk, and an else branch to connect every other stage to q[i-1]. A generate if avoids writing q[-1], which an expression like (i == 0) ? clk : q[i-1] would contain for stage 0. See Verilog generate block.
Solution
module ripple_n #(parameter N = 4) (
input clk,
input rstn,
output [N-1:0] out
);
wire [N-1:0] q, qn;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : gen_stage
if (i == 0) begin : first
// Stage 0: clocked by the system clock
dff u_dff (.d(qn[i]), .clk(clk), .rstn(rstn), .q(q[i]), .qn(qn[i]));
end else begin : rest
// Stage i: clocked by the q output of stage i-1
dff u_dff (.d(qn[i]), .clk(q[i-1]), .rstn(rstn), .q(q[i]), .qn(qn[i]));
end
end
endgenerate
assign out = qn; // q counts down, so qn counts up
endmodule
With N = 4, this builds the same circuit as ripple. With N = 15, it divides the clock by 215 = 32768, which turns a 32.768 kHz crystal into a 1 Hz tick. The worst-case settling time grows to 15 x tcq, which is acceptable at such a slow rate.
Summary
In this tutorial, you learned:
- A ripple counter clocks only its first stage from the system clock; each later stage is clocked by the previous stage's output
- Each stage is a D flip-flop with
qnfed back tod, so it toggles and divides its clock by 2 - Clocking on the rising edge of the previous
qmakesqcount down andqncount up - With the output taken from
qn, this counter shows F during reset and 0 after the first clock edge - The output settles N x tcq after the clock edge and passes through glitching intermediate values
- Ripple counters are small and low-power, but each stage is a separate generated clock
- Use synchronous counters for logic that decodes or samples the count; keep ripple counters for clock division
