Verilog Task

A Verilog task is a named, reusable block of procedural code that can take inputs, return any number of results through output and inout arguments, and, unlike a function, contain timing controls such as # delays, @ event controls and wait. Tasks are used mostly in testbenches, to package sequences that take simulation time, such as driving a bus transaction or applying a reset.

12 min read | Beginner Level

What You'll Learn

• How to declare and call a task, with inputs, outputs and timing controls
• How static and automatic tasks differ when calls overlap
• When to use a task instead of a function, and what tasks synthesize into
• How to stop a running task with disable, and avoid common task bugs

Syntax

A task can declare its arguments in the body (Style 1) or in a port list after the name (Style 2). Arguments can be input, output or inout, and a task can also have no arguments at all.

// Style 1
task [name];
	input  [port_list];
	inout  [port_list];
	output [port_list];
	begin
		[statements]
	end
endtask

// Style 2
task [name] (input [port_list], inout [port_list], output [port_list]);
	begin
		[statements]
	end
endtask

// Empty port list
task [name] ();
	begin
		[statements]
	end
endtask

• name - The task name, used to call it (required)
• input - Values copied into the task when it is called
• output - Values copied out to the caller's variables when the task finishes
• inout - Copied in at the call and copied out at the end
• statements - The task body; it may contain delays, event controls and calls to other tasks and functions

The empty parentheses in task name (); are SystemVerilog syntax. In Verilog, a task without arguments is declared as task name; and called as name;. Most simulators accept both.

A task is called as a statement on its own, not as part of an expression, because it does not return a value. Each argument in the call is matched to the task's arguments in the order they were declared.

Static Task

This task adds two 8-bit values and returns the result through an output argument. Both declaration styles below describe the same task.

	task sum (input [7:0] a, b, output [7:0] c);
		begin
			c = a + b;
		end
	endtask
// or
	task sum;
		input  [7:0] a, b;
		output [7:0] c;
		begin
			c = a + b;
		end
	endtask

	reg [7:0] x, y, z;

	initial begin
		x = 3;
		y = 4;
		sum (x, y, z);    // After the call, z = 7
	end

By default, a Verilog task is static: there is only one copy of its arguments and internal variables, and every call uses that same copy. If two calls of the same task run at the same time, for example from two initial blocks, they read and write the same variables. This example shows the effect:

module tb;

  initial display();
  initial display();
  initial display();
  initial display();

  // This is a static task
  task display();
    integer i = 0;
    i = i + 1;
    $display("i=%0d", i);
  endtask
endmodule

xcelium> run
i=1
i=2
i=3
i=4
xmsim: *W,RNQUIE: Simulation is complete.

All four calls share one variable i. In a static task, the initial value = 0 is applied only once, at the start of simulation, so each call adds 1 to the value left by the previous call.

Automatic Task

Declaring a task automatic gives every call its own copy of the task's arguments and variables, created when the call starts. Calls that overlap in time no longer interfere with each other.

module tb;

  initial display();
  initial display();
  initial display();
  initial display();

  // Note that the task is now automatic
  task automatic display();
    integer i = 0;
    i = i + 1;
    $display("i=%0d", i);
  endtask
endmodule

xcelium> run
i=1
i=1
i=1
i=1
xmsim: *W,RNQUIE: Simulation is complete.

Each call now creates a new i, initialized to 0, so every call prints 1.

Declaring a variable with an initial value inside a task, as in integer i = 0;, is SystemVerilog syntax, and these examples rely on its rule that a static variable is initialized once while an automatic one is initialized on every call. In Verilog, declare integer i; and assign it in the task body.

Using Tasks in Testbenches

The main use of tasks is to package a timed sequence of signal changes, so the stimulus code reads as a list of operations instead of a list of signal assignments. This testbench task performs one write on a simple register interface:

module tb;
  reg        clk = 0;
  reg        wr_en;
  reg  [7:0] wr_addr, wr_data;

  always #5 clk = ~clk;

  // Drive one write transaction: one clock cycle with wr_en high
  task write_reg (input [7:0] addr, input [7:0] data);
    begin
      @(posedge clk);          // Wait for a clock edge: allowed in a task
      wr_en   <= 1'b1;         // Drive module-level signals directly
      wr_addr <= addr;
      wr_data <= data;
      @(posedge clk);
      wr_en   <= 1'b0;         // End of the transaction
    end
  endtask

  initial begin
    wr_en = 0;
    write_reg(8'h10, 8'hA5);   // Each call takes two clock cycles
    write_reg(8'h14, 8'h3C);
    #20 $finish;
  end
endmodule

The task drives wr_en, wr_addr and wr_data directly instead of through output arguments. A task can read and write any variable of the module it is declared in, and the signals change at the moment of each assignment, which is what a bus interface needs.

Tasks in Synthesizable Code

A task can be used in synthesizable RTL if it contains no timing controls. Like a function, it is inlined at each call: synthesis copies its body into the calling always block, so each call builds its own logic. Because a function is simpler and can be used in expressions, most designers use functions for synthesizable code and keep tasks for testbenches. See Verilog Functions.

Global tasks

A task declared outside all modules can be called from any module in the same compilation unit:

// This task is outside all modules
task display();
  $display("Hello World !");
endtask

module des;
  initial begin
    display();
  end
endmodule

xcelium> run
Hello World !
xmsim: *W,RNQUIE: Simulation is complete.

Declaring a task outside a module is a SystemVerilog feature. In Verilog, every task must be declared inside a module. To share one task between several modules, put it in a separate file and add it to each module with `include.

If the task is declared inside module des, it is local to that module. Another module can still call it with a hierarchical reference through the instance name:

module tb;
	des u0();

	initial begin
		u0.display();  // Reached with a hierarchical name, because 'tb' has no task called display
	end
endmodule

module des;
	initial begin
		display(); 	// Task definition is local to the module
	end

	task display();
		$display("Hello World");
	endtask
endmodule

xcelium> run
Hello World
Hello World
xmsim: *W,RNQUIE: Simulation is complete.

The message appears twice: once from the initial block inside des, and once from tb calling u0.display(). See Verilog Hierarchical Reference Scope for more on hierarchical names.

Difference between function and task

The compiler enforces these rules. Here a function contains a #10 delay:

module tb;
  reg signal;

  initial wait_for_1(signal);

  function wait_for_1(reg signal);
    #10;
  endfunction
endmodule

    #10;
    |
xmvlog: *E,BADFCN (testbench.sv,7|4): illegal time/event control statement within a function or final block or analog initial block [10.3.4(IEEE)].

To wait inside a reusable block of code, declare it as a task instead.

Disable Task

A running task, or a named block inside it, can be stopped with the disable statement. Execution then continues with the statement after the disabled block.

module tb;

  initial display();

  initial begin
  	// After 50 time units, disable a particular named
  	// block T_DISPLAY inside the task called 'display'
    #50 disable display.T_DISPLAY;
  end

  task display();
    begin : T_DISPLAY
      $display("[%0t] T_Task started", $time);
      #100;
      $display("[%0t] T_Task ended", $time);
    end

    begin : S_DISPLAY
      #10;
      $display("[%0t] S_Task started", $time);
      #20;
      $display("[%0t] S_Task ended", $time);
    end
  endtask
endmodule

xcelium> run
[0] T_Task started
[60] S_Task started
[80] S_Task ended
xmsim: *W,RNQUIE: Simulation is complete.

Block T_DISPLAY starts at 0 and waits for 100 time units, but it is disabled at 50, so its "ended" message never prints. The task continues with S_DISPLAY at 50, which waits 10 more units and starts at 60, then ends at 80. Writing disable display; instead would stop the whole task, including S_DISPLAY.

Common Beginner Mistakes

module tb;
  reg clk = 0;
  reg rstn;

  always #5 clk = ~clk;

  // Hold reset for a given number of clock cycles, then release it
  task apply_reset (input integer cycles);
    begin
      rstn = 1'b0;                     // Assert reset immediately
      repeat (cycles) @(posedge clk);  // Timing control: allowed in a task
      rstn <= 1'b1;                    // Release just after the last edge
    end
  endtask

  initial begin
    apply_reset(5);                    // Reset held for 5 rising edges
    // ... rest of the test ...
    #100 $finish;
  end
endmodule