What are all different applications of FIFO?

FIFOs (First-In-First-Out) are used in a wide range of applications where data needs to be buffered or stored temporarily. Some of the most common applications of FIFOs include:

  • Memory and data buffering: FIFOs are commonly used for buffering data in memory or I/O controllers to ensure a smooth flow of data between different systems or devices.
  • Network routing and switching: In networking equipment such as routers and switches, FIFOs are used to store packets of data from different sources and route them to their destination in the correct order.
  • Multimedia applications: In multimedia applications such as audio and video processing, FIFOs are used to buffer data streams to ensure smooth playback without any glitches or interruptions.
  • Real-time applications: In real-time systems such as industrial automation and control systems, FIFOs are used to synchronize the flow of data and ensure that it is processed in real-time without any delays.
  • Data acquisition: FIFOs are used in data acquisition systems to temporarily store data from sensors, ADCs, and other data sources before it is processed or transmitted.
  • Graphics processing: In graphics processing units (GPUs), FIFOs are used to temporarily store data such as rendering commands and pixel data before it is processed and displayed on a screen.

Overall, FIFOs have a wide range of applications in different fields where data needs to be stored and processed in a controlled and efficient manner.

How can you define strength in Verilog

In Verilog, strength is a measure of the signal's electrical characteristics. It indicates how strongly the signal is driven or resisted by the driver. Verilog defines two types of signal strengths, which are:

  • Charge Strength : This is used only with trireg nets and is used to model charge storage which specifies the relative size of the capacitance i.e. small, medium or large.

  • Drive Strength : This indicates the strength of the logic values on the output terminals of the gate instance, and can be of strength1 specified by supply1, strong1, pull1 and weak1 or strength0 specified by suppy0, strong0, pull0 and weak0.

Design divide-by-5 module.

A divide-by-5 module takes an input clock signal and produces an output that is 1/5th the frequency of the input signal. Design a mod-5 counter, and take the output from the flop that is high for 2 clocks and feed it to a negative edge triggered FF. Then do a logical OR of the delayed version with the original to get the required clock output.

module clk_div5 (input clk, rstn, output clk50);
  wire clkA;
  reg clkB;
  reg [2:0] count;
  always @(posedge clk or negedge rstn) begin
    if (!rstn)
			count <= 0;
    else if (count == 4)
			count <= 0;
			count <= count + 1;
	assign clkA = count[1];

	always@(negedge clk)
		clkB <= clkA;

	assign clk50 = clkA | clkB;

Write a Verilog code for 5:1 MUX

A 5:1 MUX selects one of five input signals and forwards it to the output based on the value of two select signals. A possible Verilog implementation for a 5:1 MUX is:

module mux_5to1 (input [4:0] data, [2:0] sel, output reg out);
  always @ (data, sel) begin
    case (sel)
      5'h0 		: out = data[0];
      5'h1 		: out = data[1];
      5'h2 		: out = data[2];
      5'h3 		: out = data[3];
      default 	: out = data[4];

The data input is a 5-bit wide vector containing the five input signals to the MUX. The sel input is a 2-bit wide vector containing the two select signals. The out output is the selected input signal.

The always block describes a combinational logic that selects the appropriate input signal based on the value of the sel vector. The case statement selects the input signal corresponding to the value of sel . This implementation assumes that there is a default value for the output signal when sel is not one of the valid selection codes.

Elaborate on the Verilog event scheduler?

The Verilog event scheduler is an essential part of the Verilog simulator, responsible for scheduling and executing events during the simulation. Events in Verilog can be either timed or procedural.

Timed events represent changes in the simulation time and are scheduled by the simulator's built-in timing mechanism. The scheduler maintains a list of timed events that are sorted by their scheduled time. When the simulator advances to a new time, the scheduler looks at the list of timed events and executes any events that are scheduled to occur at the current time or earlier. Timed events can be scheduled using the # delays or using statements such as @ or wait.

Procedural events represent changes in the simulation state that are triggered by procedural statements such as always, initial, and assign. These events are scheduled based on the hierarchy and sensitivity lists of the modules in the design. Whenever a procedural event is triggered, the scheduler adds the corresponding changes to the list of timed events.

Read more on Verilog Scheduling Semantics.

Difference between dual port ram and FIFO.

Dual Port RAM and FIFO (First-In-First-Out) are both memory elements used in digital designs, but they have some key differences in their architecture, functionality, and use cases.

  • Architecture: Dual Port RAM has two separate ports, one for read and one for write access, allowing simultaneous access to different addresses in the memory. FIFO, on the other hand, is implemented as a circular shift register with two pointers (Read and Write pointers) which indicate when the FIFO is full or empty.
  • Functionality: An address in Dual Port RAM can be accessed in consecutive cycles whereas a FIFO does not have an address and hence data at the same location can be written or read after a wrap around.
  • Timing control: Dual Port RAM allows simultaneous access to different locations, but it requires proper timing control to avoid issues like read-after-write hazards and write-after-write clashes. FIFOs, on the other hand, are optimized for timing control and provide built-in circuitry to detect overflow and underflow conditions.
  • Handshaking: Dual Port RAM provides control signals like Read/Write enable signals, address signals, and output data signals for handshaking between different modules, whereas FIFOs provide control signals like Read/Write pointer signals and status signals to detect buffer overflow/underflow conditions.

In summary, Dual Port RAM is a more general-purpose memory element that supports simultaneous access to different memory locations, while FIFO is a specialized memory element that is best suited for buffering and rate conversion between devices with different data rates or clock domains.

Write Verilog code to store fractional number

In Verilog, fractional decimal numbers are typically stored as fixed-point numbers, where a fixed number of bits are allocated to represent the integer and fractional parts of the number. One common format for fixed-point numbers is Qm.n, where m+n is the total number of bits and n is the number of bits allocated to represent the fractional part. Here's an example Verilog code to store a Q7.4 fixed-point number:

module fixed_point_example();

  reg [6:0] integer_part;         // 7 bits for integer part
  reg [3:0] fractional_part;      // 4 bits for fractional part

  reg [10:0] fixed_point_number;  // 11 bits for Q7.4 number

  initial begin
    integer_part = 5;
    fractional_part = 8;          // This is 0.5 in Q7.4 format

    fixed_point_number = {integer_part, fractional_part}; // Concatenate integer and fractional parts
    $display("Fixed-point number = %d.%d", fixed_point_number[10:4], fixed_point_number[3:0]); // Display as decimal number


In this code, the reg declarations define three registers to store the integer part, fractional part, and fixed-point number. The integer_part register has 7 bits to represent the integer part of the number, and the fractional_part register has 4 bits to represent the fractional part of the number in Q7.4 format.

What are synchronous and asynchronous resets ?

Most practical sequential elements require a reset signal to have a known initial state on startup.

Asynchronous reset forces the output low immediately. It requires gating both the data and the feedback to force the reset independent of the clock.

// "rstn" added to the sensitivity list so that it evaluates the 
// if condition immediately on the negedge of "rstn". At the negedge 
// of rstn, its value is 0.
always @ (posedge clk and negedge rstn) begin
	if (rstn) begin
		out <= 0;
    end else begin
    	// rest of the logic

Synchronous reset waits for the clock to force the output low, and it simply needs an AND between the data input and reset signal.

// Here, the if condition is evaluated only on the posedge of "clk" 
// and the block is reset if "rstn" is found to be 0
always @ (posedge clk) begin
	if (rstn) begin
		out <= 0;
    end else begin
    	// rest of the logic

Explain the concept of time borrowing

Time borrowing is a mechanism in which a latch based design effectively uses the transparency between two adjacent latches to meet the propagation delay between them.

             L1             ___           L2
         .--------.      --'   '--.    .--------.
in ------| d    q |---- (pd = 8ns  )---| d    q |
         |        |      --.   .--'    |        |
         |   en   |         '-'        |   en   |
         '--------'                    '--------'
clk  ---------'                             |
~clk  --------------------------------------'

Enables for the two latches shown above are opposite in polarity. L1 is enabled during the ON period of clk while L2 is enabled during the OFF period of clk . Assume that the delay for d -> q and en -> q is 0ns, the propagation delay for the combinational cloud between the latches is 8ns, and the clock period is 10ns. Time borrowed is 2ns.

                  __________            __________
clk   |__________|          |__________|          |__________
       __________            __________            __________
~clk  |          |__________|          |__________|

      |<------ 10 ns ------>|
      |<-- Tpd=8ns-->|
                     |< 2ns>| (time borrowed)