Verilog Ports

Port Name Uniqueness: It is illegal to use the same name for multiple ports. Each port must have a unique identifier within a module.

input  aport;    // First declaration - valid
input  aport;    // Error - already declared
output aport;    // Error - already declared

Signed Ports

The signed attribute can be attached to a port declaration or a net/reg declaration or both. This is critical for correct arithmetic operations--unsigned and signed values behave differently in comparisons and arithmetic.

Default: Unsigned

Implicit nets are by default unsigned:

module my_module (
  input a,         // Unsigned by default
  input b,         // Unsigned by default
  output c         // Unsigned by default
);

  // ports a, b, and c are by default unsigned
endmodule

Signed Port Declaration

If either the net/reg declaration or the port declaration has a signed attribute, then the signal shall be considered signed:

module signed_example (
  input signed a, b,       // Declare ports as signed in port list
  output c
);

  wire a, b;               // a, b inherit 'signed' from port declaration
  reg signed c;            // c is signed from reg declaration

endmodule

When to Use Signed Ports: Use signed ports when performing arithmetic that involves negative numbers, such as digital signal processing (DSP), coordinate calculations, or signed comparisons. For example, a 2's complement signed 4-bit value can represent -8 to +7, while unsigned represents 0 to 15.

Port Variations Across Verilog Standards

Verilog has evolved through several IEEE standard revisions, and port declaration syntax has changed significantly between versions.

Verilog-1995 Style (Non-ANSI)

The original IEEE 1364-1995 standard required port names to be listed in the module header, with directions and types declared separately inside the module body:

// Verilog-1995: Port list first, directions declared later
module test (a, b, c);                 // List port names only

  input  [7:0] a;                      // inputs "a" and "b" are wires
  input  [7:0] b;
  output [7:0] c;                      // output "c" by default is a wire

  // Still, you can declare them again as wires to avoid confusion
  wire [7:0] a;
  wire [7:0] b;
  wire [7:0] c;
endmodule


module test (a, b, c);

  input  [7:0] a, b;                   // Multiple inputs on one line
  output [7:0] c;                      // By default c is of type wire

  // port "c" is changed to a reg type (needed for always blocks)
  reg [7:0] c;
endmodule

Verilog-1995 Characteristics:

• Port names listed in module header without types
• Port directions (input/output/inout) declared inside module
• Port can be redeclared with a different data type (wire vs reg)
• More verbose but allows flexible type changes

Verilog-2001 Style (ANSI-C)

ANSI-C style port naming was introduced in IEEE 1364-2001 and allowed the type and direction to be specified directly inside the port list:

// Verilog-2001: Direction and type in port list (ANSI-C style)
module test (
  input [7:0]  a,                      // 8-bit input
               b,                      // "b" is also considered an 8-bit input (continues from previous line)
  output [7:0] c                       // 8-bit output
);

  // Design content
endmodule


module test (
  input wire [7:0]  a,                 // Explicit wire type (redundant, wire is default)
  input wire [7:0]  b,
  output reg [7:0]  c                  // Output driven by reg (for use in always blocks)
);

  // Design content
endmodule

Verilog-2001 Characteristics:

• Port direction, type, and width declared in one place (more concise)
• Matches modern C/C++/SystemVerilog syntax style
• Easier to read--all port information visible at module header
• Cannot redeclare ports if type is specified in port list

Complete vs. Incomplete Declarations

If a port declaration includes a net or variable type (wire, reg), then that port is considered to be completely declared. It is illegal to redeclare the same port in a net or variable type declaration:

module test (
  input [7:0]      a,                  // a, e are implicitly declared of type wire
  output reg [7:0] e                   // e is explicitly declared as reg
);

  wire signed [7:0] a;                 // OKAY - 'a' has no net type in the port list, so this completes its declaration
  wire [7:0] e;                        // ILLEGAL - declaration of 'e' is already complete

  // Rest of the design code
endmodule

However, if the port declaration does not include a net or variable type, then the port can be declared again in a net or variable type declaration:

module test (
  input  [7:0] a,                      // No type specified - incomplete declaration
  output [7:0] e                       // No type specified - incomplete declaration
);

  reg [7:0] e;                         // OKAY - net_type was not declared before

  // Rest of the design code
endmodule

Verilog-1995 vs. Verilog-2001 Comparison

Common Beginner Mistakes

// WRONG - output is wire by default, can't be driven from always block
module counter (
  input clk,
  output [3:0] count           // Implicit wire type
);

  always @(posedge clk) begin
    count <= count + 1;        // ERROR: Cannot assign to wire from procedural block
  end
endmodule

// CORRECT - output declared as reg
module counter (
  input clk,
  output reg [3:0] count       // Explicitly reg type
);

  always @(posedge clk) begin
    count <= count + 1;        // OK: reg can be assigned in always block
  end
endmodule

// WRONG - attempting to redeclare complete port declarations
module my_module (
  input wire [7:0] a,          // Complete declaration (type specified)
  output reg [7:0] b           // Complete declaration
);

  wire [7:0] a;                // ILLEGAL - 'a' already completely declared
  reg [7:0] b;                 // ILLEGAL - 'b' already completely declared

endmodule

// CORRECT - ports incomplete in port list, completed inside module
module my_module (
  input [7:0] a,               // Incomplete (no type)
  output [7:0] b               // Incomplete (no type)
);

  // Now you can complete the declarations
  wire [7:0] a;                // OK - completes declaration of 'a'
  reg [7:0] b;                 // OK - completes declaration of 'b' as reg

endmodule

// WRONG - comparing signed and unsigned incorrectly
module comparator (
  input [7:0] a,               // Unsigned (default)
  input signed [7:0] b,        // Signed
  output greater               // Result of a > b
);

  assign greater = (a > b);    // Incorrect: mixed signedness comparison

endmodule

// CORRECT - consistent signedness
module comparator (
  input signed [7:0] a,        // Both signed
  input signed [7:0] b,        // Both signed
  output greater
);

  assign greater = (a > b);    // Correct: signed comparison (-1 < 127)

endmodule

// WRONG - driving inout without tri-state
module bad_inout (
  inout [7:0] data
);

  reg [7:0] internal_data;

  assign data = internal_data;  // ERROR: Always driving, no tri-state!

endmodule

// CORRECT - inout with tri-state control
module good_inout (
  inout [7:0] data,
  input output_enable
);

  reg [7:0] internal_data;

  // Tri-state: drive when enabled, high-Z when disabled
  assign data = output_enable ? internal_data : 8'bz;

endmodule