Verilog Blocking & Non-Blocking

Understanding the difference between blocking (=) and non-blocking (<=) assignments is critical for writing correct Verilog code. The wrong choice can lead to simulation mismatches, race conditions, and synthesized hardware that behaves differently than your testbench.

8 min read | Beginner to Intermediate

What You'll Learn

• Master the execution semantics of blocking (=) versus non-blocking (<=) assignments
• Understand time-step evaluation and how assignments are scheduled in Verilog simulators
• Apply the correct assignment type for combinational logic, sequential logic, and testbenches
• Recognize and avoid race conditions caused by improper mixing of assignment types

Assignment Types Comparison

Blocking Assignments

Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. Each statement must complete before the next one executes. However, this will not prevent execution of statements that run in a parallel block.

module tb;
  reg [7:0] a, b, c, d, e;

  initial begin
    a = 8'hDA;                                            // Execute first
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // Then display (b, c still unassigned)
    b = 8'hF1;                                            // Then assign b
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // Display again (c still unassigned)
    c = 8'h30;                                            // Finally assign c
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // Display all assigned values
  end

  initial begin                                          // This block runs in parallel with the first block
    d = 8'hAA;                                           // Execute first in this block
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);     // Display (e still unassigned)
    e = 8'h55;                                           // Then assign e
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);     // Display both assigned
  end
endmodule

Note that there are two initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variables b and c are 8'hxx in the first display statement because their assignments have not been executed yet when the first $display is called.

ncsim> run
[0] a=0xda b=0xx c=0xx
[0] a=0xda b=0xf1 c=0xx
[0] a=0xda b=0xf1 c=0x30
[0] d=0xaa e=0xx
[0] d=0xaa e=0x55
ncsim: *W,RNQUIE: Simulation is complete.

Blocking Assignments with Delays

In the next example, we'll add a few delays into the same set of statements to see how it behaves.

module tb;
  reg [7:0] a, b, c, d, e;

  initial begin
    a = 8'hDA;                                            // Execute at time 0
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
    #10 b = 8'hF1;                                        // Wait 10ns, then execute
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // Execute at time 10
    c = 8'h30;                                            // Execute immediately after b
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // Still at time 10
  end

  initial begin
    #5 d = 8'hAA;                                         // Wait 5ns, then execute
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);      // Execute at time 5
    #5 e = 8'h55;                                         // Wait another 5ns (total 10ns)
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);      // Execute at time 10
  end
endmodule

ncsim> run
[0] a=0xda b=0xx c=0xx
[5] d=0xaa e=0xx
[10] a=0xda b=0xf1 c=0xx
[10] a=0xda b=0xf1 c=0x30
[10] d=0xaa e=0x55
ncsim: *W,RNQUIE: Simulation is complete.

Blocking Assignments in Testbenches: Use blocking assignments in testbenches when you want sequential stimulus generation. Each assignment completes before the next begins, making the test flow predictable and easy to debug.

Non-Blocking Assignments

Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a <= symbol. It's interesting to note that the same symbol is used as a relational operator in expressions (less than or equal), and as an assignment operator in the context of a non-blocking assignment.

If we take the first example from above and replace all = symbols with a non-blocking assignment operator <=, we'll see a significant difference in the output.

module tb;
  reg [7:0] a, b, c, d, e;

  initial begin
    a <= 8'hDA;                                           // Schedule assignment to 'a' for end of time-step
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // 'a' not updated yet!
    b <= 8'hF1;                                           // Schedule assignment to 'b' for end of time-step
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // 'a', 'b' not updated yet!
    c <= 8'h30;                                           // Schedule assignment to 'c' for end of time-step
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // None updated yet!
  end                                                     // End of time-step: Now a, b, c get their values

  initial begin
    d <= 8'hAA;                                           // Schedule assignment to 'd'
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);      // 'd' not updated yet!
    e <= 8'h55;                                           // Schedule assignment to 'e'
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);      // 'd', 'e' not updated yet!
  end                                                     // End of time-step: Now d, e get their values
endmodule

Notice that all the $display statements printed 'hx. The reason for this behavior lies in the way non-blocking assignments are executed:

1. The RHS of every non-blocking statement at a particular time-step is evaluated and captured
2. Execution immediately moves to the next statement
3. The captured RHS value is assigned to the LHS variable only at the end of the time-step

ncsim> run
[0] a=0xx b=0xx c=0xx
[0] a=0xx b=0xx c=0xx
[0] a=0xx b=0xx c=0xx
[0] d=0xx e=0xx
[0] d=0xx e=0xx
ncsim: *W,RNQUIE: Simulation is complete.

So, if we break down the execution flow of the above example we'll get something like what's shown below:

|__ Spawn Block1: initial
|   |___ Time #0ns : a <= 8'hDA, is non-blocking so note value of RHS (8'hDA) and execute next step
|   |___ Time #0ns : $display() is blocking, so execute this statement: But a hasn't received new values so a=8'hx
|   |___ Time #0ns : b <= 8'hF1, is non-blocking so note value of RHS (8'hF1) and execute next step
|   |___ Time #0ns : $display() is blocking, so execute this statement. But b hasn't received new values so b=8'hx
|   |___ Time #0ns : c <= 8'h30, is non-blocking so note value of RHS (8'h30) and execute next step
|   |___ Time #0ns : $display() is blocking, so execute this statement. But c hasn't received new values so c=8'hx
|   |___ End of time-step and initial block, assign captured values into variables a, b, c
|
|__ Spawn Block2: initial
|   |___ Time #0ns : d <= 8'hAA, is non-blocking so note value of RHS (8'hAA) and execute next step
|   |___ Time #0ns : $display() is blocking, so execute this statement: But d hasn't received new values so d=8'hx
|   |___ Time #0ns : e <= 8'h55, is non-blocking so note value of RHS (8'h55) and execute next step
|   |___ Time #0ns : $display() is blocking, so execute this statement. But e hasn't received new values so e=8'hx
|   |___ End of time-step and initial block, assign captured values into variables d and e
|
|__ End of simulation at #0ns

Non-Blocking Assignments with Delays

Next, let's use the second example and replace all blocking statements with non-blocking assignments.

module tb;
  reg [7:0] a, b, c, d, e;

  initial begin
    a <= 8'hDA;                                           // Schedule for end of time-step 0
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // 'a' not yet updated
    #10 b <= 8'hF1;                                       // Wait 10ns, then schedule for end of time-step 10
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // 'b' not yet updated (but 'a' is now 0xDA)
    c <= 8'h30;                                           // Schedule for end of time-step 10
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);  // 'b', 'c' not yet updated
  end

  initial begin
    #5 d <= 8'hAA;                                        // Wait 5ns, then schedule for end of time-step 5
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);      // 'd' not yet updated
    #5 e <= 8'h55;                                        // Wait 5ns more (total 10ns), schedule for end of time-step 10
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);      // 'e' not yet updated (but 'd' is now 0xAA)
  end
endmodule

Once again we can see that the output is different than what we got before with blocking assignments.

ncsim> run
[0] a=0xx b=0xx c=0xx
[5] d=0xx e=0xx
[10] a=0xda b=0xx c=0xx
[10] a=0xda b=0xx c=0xx
[10] d=0xaa e=0xx
ncsim: *W,RNQUIE: Simulation is complete.

If we break down the execution flow we'll get something like what's shown below:

|__ Spawn Block1 at #0ns: initial
|   |___ Time #0ns : a <= 8'hDA, is non-blocking so note value of RHS (8'hDA) and execute next step
|   |___ Time #0ns : $display() is blocking, so execute this statement: But a hasn't received new values so a=8'hx
|   |___ End of time-step : Assign captured value to variable a, and a is now 8'hDA
|   |___ Wait until time advances by 10 time-units to #10ns
|
|   |___ Time #10ns : b <= 8'hF1, is non-blocking so note value of RHS (8'hF1) and execute next step
|   |___ Time #10ns : $display() is blocking, so execute this statement. But b hasn't received new values so b=8'hx
|   |___ Time #10ns : c <= 8'h30, is non-blocking so note value of RHS (8'h30) and execute next step
|   |___ Time #10ns : $display() is blocking, so execute this statement. But c hasn't received new values so c=8'hx
|   |___ End of time-step and initial block, assign captured values into variables b, c
|
|__ Spawn Block2 at #0ns: initial
|   |___ Wait until time advances by 5 time-units to #5ns
|
|   |___ Time #5ns : d <= 8'hAA, is non-blocking so note value of RHS (8'hAA) and execute next step
|   |___ Time #5ns : $display() is blocking, so execute this statement: But d hasn't received new values so d=8'hx
|   |___ End of time-step : Assign captured value to variable d, and d is now 8'hAA
|   |___ Wait until time advances by 5 time-units to #10ns
|
|   |___ Time #10ns : e <= 8'h55, is non-blocking so note value of RHS (8'h55) and execute next step
|   |___ Time #10ns : $display() is blocking, so execute this statement. But e hasn't received new values so e=8'hx
|   |___ End of time-step and initial block, assign captured values to variable e, and e is now 8'h55
|
|__ End of simulation at #10ns

// Combinational logic - use blocking
always @(*) begin
  temp = a & b;                    // Blocking: intermediate value
  c = temp | d;                    // Blocking: final output depends on temp
end

// Sequential logic - use non-blocking
always @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    q1 <= 1'b0;                    // Non-blocking: parallel register updates
    q2 <= 1'b0;                    // Non-blocking: models flip-flop behavior
  end else begin
    q1 <= d;                       // Non-blocking: avoids race conditions
    q2 <= q1;                      // Non-blocking: creates register chain
  end
end

// WRONG - creates race conditions
always @(posedge clk) begin
  q1 = d;       // Blocking in sequential block
  q2 = q1;      // q2 gets NEW value of q1, not previous!
end

// CORRECT - models register chain
always @(posedge clk) begin
  q1 <= d;      // Schedule assignment
  q2 <= q1;     // Captures OLD value of q1
end

// WRONG - creates synthesis mismatch
always @(*) begin
  temp <= a & b;      // Non-blocking in combinational
  c <= temp | d;      // May not see updated temp!
end

// CORRECT - immediate evaluation
always @(*) begin
  temp = a & b;       // Blocking: temp updated immediately
  c = temp | d;       // c sees new temp value
end

// WRONG - unpredictable behavior
always @(posedge clk) begin
  if (condition1)
    counter = counter + 1;      // Blocking
  else
    counter <= counter - 1;     // Non-blocking
end

// CORRECT - consistent assignment type
always @(posedge clk) begin
  if (condition1)
    counter <= counter + 1;     // Non-blocking
  else
    counter <= counter - 1;     // Non-blocking
end

// WRONG - assumes block execution order
always @(posedge clk) begin
  data_ready = 1'b1;            // Blocking in first block
end

always @(posedge clk) begin
  if (data_ready)               // Reads data_ready from parallel block
    process_data = data;        // May see old or new value!
end

// CORRECT - deterministic behavior
always @(posedge clk) begin
  data_ready <= 1'b1;           // Non-blocking: updates at end of time-step
end

always @(posedge clk) begin
  if (data_ready)               // Reads previous cycle's value
    process_data <= data;       // Deterministic pipeline behavior
end