Verilog $stop $finish

The system tasks $stop and $finish both stop a simulation, but for different purposes: $stop pauses it so that you can look around, and $finish ends it for good.

A simulation normally ends by itself when there is nothing left to do: every initial block has executed its last statement and no more events are scheduled. Most testbenches, however, contain processes that never run out of events, such as a clock generator always #5 clk = ~clk; or a forever loop. Without an explicit $finish, such a simulation would keep advancing time forever.

8 min read | Beginner Level

What You'll Learn

• How $stop pauses a simulation for interactive debugging
• How $finish ends a simulation, and what its optional argument prints
• How testbenches use $finish for end-of-test reports and timeout watchdogs
• Common mistakes that make a simulation hang or end too early

$stop

$stop suspends the simulation, much like a breakpoint in a software debugger. Simulation time stops advancing and the simulator shows its interactive prompt. All signal values are kept, so you can inspect variables, look at waveforms or change values, and then continue the run from exactly the same point.

$stop([N]);

// where N is
// 0   :   Prints nothing
// 1   :   Prints simulation time and location
// 2   :   Prints simulation time, location, and statistics about the memory
//         and central processing unit (CPU) time used in simulation

Without an argument, $stop behaves as $stop(1). The command to resume a paused simulation is specific to each simulator, often something like run or cont typed at the prompt, so check your simulator's manual.

module tb;

  reg [3:0] counter;

  initial begin
    counter = 0;
    #10 counter = counter + 1; // Increment after 10 time units
    $display("Counter value before stop: %b", counter);

    $stop; // Simulation pauses here

    // This line will not execute until the simulation is resumed
    #10 counter = counter + 1;
    $display("Counter value after stop: %b", counter);
  end
endmodule

The counter is incremented at 10 ns and its value is printed. The simulation then pauses at $stop, at time 10. Nothing else happens until you resume it; then the counter is incremented again at 20 ns and printed. The output looks like this, with the exact pause message depending on the simulator:

Counter value before stop: 0001
(simulator prints the stop time and location, and waits at its prompt)
Counter value after stop: 0010

$finish

$finish ends the simulation completely: the simulator stops, closes its output files, and returns control to the operating system. It is used when a test has finished, or when the testbench detects an error so serious that continuing makes no sense. It takes the same optional argument as $stop.

$finish([N]);

// where N is
// 0   :   Prints nothing
// 1   :   Prints simulation time and location
// 2   :   Prints simulation time, location, and statistics about the memory
//         and central processing unit (CPU) time used in simulation

module tb;

  initial begin

    // Some simulation code...
    #10 $display("Waited to 10 units");

    // Terminate simulation and print a diagnostic message
    $finish(1);

    // This delay will never be executed in simulation because it will be
    // terminated by the line before
    #100;
  end

endmodule

The message is printed at time 10, and the simulation ends right there with a short note giving the time and location of the $finish. The #100 after it is never reached. $finish ends the whole simulation, not just the block that calls it, so every other initial and always block stops too.

Ending a Test with $finish

In a self-checking testbench, $finish usually comes right after the final report, in the block that runs the stimulus:

initial begin
  run_all_tests;                      // Task with the stimulus and checks
  if (errors == 0)
    $display ("TEST PASSED");
  else
    $display ("TEST FAILED: %0d errors", errors);
  $finish;
end

A second block acts as a watchdog. If the design hangs, for example because a handshake never completes, the main block never reaches its $finish, and the watchdog ends the simulation with an error instead of letting it run forever:

initial begin
  #1_000_000;                         // Longer than any test should take
  $display ("ERROR: Timeout at %0t, test did not finish", $time);
  $finish;
end

Difference between $stop and $finish

$stop is a tool for debugging, while $finish is the normal way to end a testbench or a simulation run.

Synthesis result: None. $stop and $finish are simulation-only system tasks and are ignored by synthesis tools. They only appear in testbenches and behavioral models.

Common Beginner Mistakes

$finish;
$display ("TEST PASSED");   // Never printed

module tb;
  reg done = 0;

  initial begin
    #300 done = 1;
  end

  initial begin
    wait (done);
    $display ("T=%0t TEST PASSED", $time);
    $finish;
  end

  initial begin
    #200;
    $display ("T=%0t ERROR: Timeout", $time);
    $finish;
  end
endmodule

T=200 ERROR: Timeout