Verilog Binary to Gray

Gray code is a binary code where each successive value differs from the previous value by only one bit. A Verilog binary to Gray converter turns an N-bit binary number into its Gray code with one XOR gate per bit: the most significant bit is copied, and every other Gray bit is the XOR of a binary bit and the bit above it.

8 min read | Beginner Level

What You'll Learn

• How Gray code differs from binary, and the rule for converting between them
• Write a parameterized binary to Gray converter in two ways
• Why both versions synthesize into the same N-1 XOR gates
• Verify the conversion exhaustively and avoid common conversion bugs

Binary and Gray Code

In binary counting, several bits can change between consecutive values, such as all four bits from 7 (0111) to 8 (1000). In Gray code, exactly one bit changes between any two consecutive values, including the wrap-around from the last value back to 0.

The conversion rule for an N-bit value is:

gray[N-1] = bin[N-1]                  // MSB is copied
gray[i]   = bin[i+1] ^ bin[i]         // for i = N-2 down to 0

Each Gray bit is 1 when the binary bit and its upper neighbor differ. For example, binary 1011 gives Gray 1, 1^0 = 1, 0^1 = 1, 1^1 = 0, which is 1110.

Implementation #1

The first version applies the rule bit by bit, using a generate loop to create one assign statement for each bit except the MSB.

module bin2gray #(parameter N=4) ( input  [N-1:0] bin,
                                   output [N-1:0] gray);

  genvar i;
  generate
    for(i = 0; i < N-1; i = i + 1) begin : gen_xor   // One XOR per bit below the MSB
      assign gray[i] = bin[i] ^ bin[i+1];
    end
  endgenerate

  assign gray[N-1] = bin[N-1];                         // MSB copied unchanged
endmodule

The loop runs only to N-2, because bin[i+1] for the MSB would refer to a bit that does not exist. The MSB is handled separately.

Hardware Schematic

For N = 4, the schematic shows three 2-input XOR gates and a direct connection from bin[3] to gray[3]. All the XOR gates work in parallel, so the delay is one gate regardless of N.

Implementation #2

The whole rule can also be written as one vector expression. Shifting bin right by one places each bit's upper neighbor in its position, with a 0 shifted into the MSB, so XORing the two produces every Gray bit at once.

module bin2gray #(parameter N=4) ( input  [N-1:0] bin,
                                   output [N-1:0] gray);

  // bin >> 1 lines up bin[i+1] with bin[i]; the shifted-in 0 leaves the MSB unchanged
  assign gray = bin ^ (bin >> 1);

endmodule

Hardware Schematic

This schematic is the elaborated, pre-optimization view, so it shows a shift operator feeding a vector XOR. That shift block is not a shift register and does not cost any gates. Shifting by a constant amount only renames wires: (bin >> 1)[i] is simply bin[i+1], and its MSB is the constant 0. After optimization, gray[N-1] = bin[N-1] ^ 0 reduces to a wire, and the result is the same N-1 XOR gates as Implementation #1.

PPA Impact: Both implementations produce identical hardware after synthesis, with the same area, power and delay. Choose between them for readability: the one-line expression is shorter, while the generate loop makes the per-bit rule visible.

Testbench

The testbench applies all 16 values of a 4-bit input and prints each binary value with its Gray code. The output should match the table at the start of this article.

module tb;
  reg  [3:0] bin;
  wire [3:0] gray;
  integer    i;

  bin2gray #(.N(4)) u0 (.bin(bin), .gray(gray));

  initial begin
    for (i = 0; i < 16; i = i + 1) begin
      bin = i;
      #1;                                   // Let the combinational output settle
      $display("bin=%b gray=%b", bin, gray);
    end
  end
endmodule

Common Beginner Mistakes

module tb_check;
  reg  [3:0] bin;
  wire [3:0] gray;
  reg  [3:0] prev_gray, diff;
  integer    i, b, ones, errors;

  bin2gray #(.N(4)) u0 (.bin(bin), .gray(gray));

  initial begin
    errors = 0;
    bin = 4'd15;  #1  prev_gray = gray;      // Start from 15 to check the wrap to 0

    for (i = 0; i < 16; i = i + 1) begin
      bin = i;  #1;
      diff = gray ^ prev_gray;               // 1 in every bit that changed
      ones = 0;
      for (b = 0; b < 4; b = b + 1)
        ones = ones + diff[b];
      if (ones != 1) begin
        $display("ERROR: %0d -> %0d changes %0d bits", (i + 15) % 16, i, ones);
        errors = errors + 1;
      end
      prev_gray = gray;
    end

    if (errors == 0) $display("PASS: every step changes exactly one bit");
    else             $display("FAIL: %0d errors", errors);
  end
endmodule