Verilog Ring Counter

A ring counter is a shift register whose last output is fed back to its first input, so the bits circulate in a closed loop. It is loaded with a single 1 and all other bits 0, and on every clock edge that 1 moves one position. In Verilog, a ring counter is a register that rotates by one bit at each clock edge.

10 min read | Beginner Level

What You'll Learn

• How a ring counter circulates a single 1 and why it produces one-hot outputs
• Write a parameterized ring counter in Verilog and initialize it correctly
• What synthesis builds from it, and how it compares with binary and Johnson counters
• How to handle illegal states with a self-correcting ring counter

What Is a Ring Counter?

A ring counter is a shift register closed into a loop. On each clock edge, every flip-flop takes the value of its neighbor, and the bit that leaves one end of the register re-enters at the other end. The feedback is a plain wire: no inverter, adder or comparator is needed.

When the register holds a single 1, that 1 travels around the loop like a ball on a track, moving one position per clock. A ring counter with N flip-flops therefore has N states and repeats every N clock cycles, so it is a Mod-N counter, as described in Verilog Mod-N counter.

How It Works

The design in this article resets to 4'b0001 and shifts to the right, with bit 0 wrapping around into bit 3:

Exactly one bit is 1 at any time. This is called one-hot encoding: each state has its own flip-flop, and the state is identified by which flip-flop holds the 1. A ring counter is the simplest one-hot circuit, and one-hot state machines use the same idea with more complex transitions between states. See Verilog FSM.

Because each output bit is high for exactly one state, no decoder is needed. A binary counter needs a comparator to detect "state 2", while a ring counter provides it directly as out[2].

Shift Direction & Initialization

The shift direction depends only on how the flip-flops are connected. Shifting right, as in this design, and shifting left are both valid. Choose the direction that makes the order of the output bits most convenient for the logic that uses them.

Initialization is the critical part. The register must start with exactly one 1:

• All zeros: if the register starts at 0000, rotating it gives 0000 forever. The counter is stuck.
• More than one 1: all the 1s circulate together. The counter still repeats, but the outputs are no longer one-hot, and any logic that assumes a single active bit fails.

The reset therefore loads a fixed one-hot value, here 1, which sets bit 0 and clears the others.

Design

module ring_ctr  #(parameter WIDTH=4)
  (
	input clk,
	input rstn,                       // Active-low synchronous reset
  	output reg [WIDTH-1:0] out
  );

  integer i;

  always @ (posedge clk) begin
      if (!rstn)
         out <= 1;                    // Load a single 1 in bit 0, zeros elsewhere
      else begin
        out[WIDTH-1] <= out[0];       // Feedback: bit 0 wraps around to the MSB
        for (i = 0; i < WIDTH-1; i=i+1) begin
          out[i] <= out[i+1];         // Every other bit takes its left neighbor
        end
      end
  end
endmodule

The for loop and the feedback assignment together rotate out right by one bit. The same rotation can be written in one line with a concatenation: out <= {out[0], out[WIDTH-1:1]};. Non-blocking assignments are required, so that every bit captures its neighbor's value from before the clock edge.

Synthesis result: The tool builds WIDTH flip-flops connected in a loop, with the reset forcing bit 0 to 1 and the others to 0. Between the flip-flops there is only wiring and the reset gating, no adder or comparator. This makes the ring counter one of the fastest counters possible, since the path from one flip-flop to the next contains almost no logic.

Testbench

The testbench uses a 20 ns clock period, holds reset for two clock edges, then runs for 15 more edges.

module tb;
  parameter WIDTH = 4;

  reg clk;
  reg rstn;
  wire [WIDTH-1:0] out;

  // Pass WIDTH to the design so both use the same value
  ring_ctr #(.WIDTH(WIDTH)) u0 (.clk (clk),
                .rstn (rstn),
                .out (out));

  always #10 clk = ~clk;        // Rising edges at 10, 30, 50, ...

  initial begin
    {clk, rstn} <= 0;

    $monitor ("T=%0t out=%b", $time, out);
    repeat (2) @(posedge clk);
    rstn <= 1;
    repeat (15) @(posedge clk);
    $finish;
  end
endmodule

ncsim> run
T=0 out=xxxx
T=10 out=0001
T=50 out=1000
T=70 out=0100
T=90 out=0010
T=110 out=0001
T=130 out=1000
T=150 out=0100
T=170 out=0010
T=190 out=0001
T=210 out=1000
T=230 out=0100
T=250 out=0010
T=270 out=0001
T=290 out=1000
T=310 out=0100
Simulation complete via $finish(1) at time 330 NS + 0

Reset loads 0001 at the first edge (10 ns). At 30 ns reset is still active, so the value does not change and $monitor prints nothing. From 50 ns, the 1 moves right by one position on every edge and wraps from bit 0 back to bit 3, repeating every four edges (80 ns).

Ring vs Johnson vs Binary Counter

A ring counter spends more flip-flops per state than any other counter, but it needs no decoding logic and has the shortest timing path. It suits a small number of states where speed or glitch-free state outputs matter. The Johnson counter doubles the number of states by inverting the feedback.

Common Beginner Mistakes

module ring_ctr_sc #(parameter WIDTH = 4) (
  input                  clk,
  input                  rstn,
  output reg [WIDTH-1:0] out
);

  always @(posedge clk) begin
    if (!rstn)
      out <= 1;
    else
      // MSB gets a 1 only when bits [WIDTH-1:1] are all zero;
      // all other bits shift right as before
      out <= {~|out[WIDTH-1:1], out[WIDTH-1:1]};
  end

endmodule