A multiplexer (mux) is a digital switch: a select input chooses which of several data inputs is connected to the single output. It is the circuit behind every "choose between" decision in hardware. A mux with n select lines can also reproduce any function of n + 1 variables, which is exactly how FPGA lookup tables work.
13 min read | Intermediate Level
What You'll Learn
- How 2-to-1 and 4-to-1 multiplexers work and how select lines address the inputs
- How to build a large multiplexer from small ones
- How to implement any Boolean function with a multiplexer
- Why a one-hot select is better served by an AND-OR structure than by a mux tree
Quick Answer: Multiplexer Sizes
| Multiplexer | Select lines | 2-to-1 muxes needed | Mux levels |
|---|---|---|---|
| 2-to-1 | 1 | 1 | 1 |
| 4-to-1 | 2 | 3 | 2 |
| 8-to-1 | 3 | 7 | 3 |
| N-to-1 | log2 N | N - 1 | log2 N |
Multiplexer proportion rules double the data inputs -> one more select line, one more mux level one more mux level -> one more mux delay on the path 2-to-1 mux, S = 0 / S = 1 -> Y = I0 / Y = I1
The 2-to-1 and 4-to-1 Multiplexer
A 2-to-1 mux copies I0 to the output when S = 0 and I1 when S = 1. In gates it is two AND gates and an OR:
Y = S'.I0 + S.I1
A 4-to-1 mux needs two select lines, because the select value counts from 0 to 3. S1 is the most significant select bit. It is a 2-to-4 decoder (see Digital Decoder Circuit) driving four AND gates and an OR:
| S1 | S0 | Y |
|---|---|---|
| 0 | 0 | I0 |
| 0 | 1 | I1 |
| 1 | 0 | I2 |
| 1 | 1 | I3 |
Y = S1'.S0'.I0 + S1'.S0.I1 + S1.S0'.I2 + S1.S0.I3
Where Are Multiplexers Used?
A register file read port is a wide mux that picks one of 32 registers, the ALU output stage selects the result of the add, logic or shift unit, and the program counter input chooses between the next sequential address and a branch target.
Building Bigger Multiplexers
Multiplexers combine into trees. An 8-to-1 mux is two 4-to-1 muxes and one 2-to-1 mux: the low select bits drive both 4-to-1 muxes, and the top select bit chooses between their outputs.
Quick Check
Q: How many select lines does a 16-to-1 mux need, and what select value routes input I11 to the output?
Show Answer
log2 16 = 4 select lines. I11 is binary 1011, so S3 S2 S1 S0 = 1011.
Implementing Functions With a Multiplexer
The 4-to-1 equation is a sum of minterms of S1 and S0 multiplied by data inputs. With constants on the data inputs, an N-to-1 mux implements any function of log2 N variables straight from its truth table. This is an FPGA lookup table: a mux tree whose data inputs are configuration bits.
A smarter trick halves the size. Use all but one variable as selects, and connect the last variable, its complement or a constant to each data input. Example: F(x, y, z) = Σm(1, 2, 6, 7) on a 4-to-1 mux, with x and y as selects:
| x y | F when z = 0 | F when z = 1 | F in terms of z | Mux input |
|---|---|---|---|---|
| 00 | 0 | 1 | z | I0 = z |
| 01 | 1 | 0 | z' | I1 = z' |
| 10 | 0 | 0 | 0 | I2 = 0 |
| 11 | 1 | 1 | 1 | I3 = 1 |
The same method scales: a 2n-to-1 mux implements any function of n + 1 variables with at most one inverter.
Where Is Multiplexer-Based Logic Used?
Each lookup table in an FPGA is a multiplexer tree over configuration memory bits, and the routing fabric uses multiplexers to select which wire drives every logic input.
Multiplexer Cells and One-Hot Selects
Standard-cell libraries contain MUX2 and MUX4 cells, usually built from transmission gates (see NMOS vs PMOS), so the data passes through one switch. A wide bus uses one mux per bit, all sharing the same select lines.
If the select is one-hot instead of binary, an AND-OR structure is smaller and faster than a mux tree, because no decoding is needed:
One-hot select, 4 data inputs Y = I0.S0 + I1.S1 + I2.S2 + I3.S3 exactly one of S0..S3 is 1, so exactly one AND term can pass data
Common Mistakes
Mistake #1: Swapping the select bits
Wrong: Wiring S1 to the least significant select pin
Right: S0 is the least significant select bit: S1 S0 = 10 picks I2.
Why? Swapped selects exchange I1 and I2 and are hard to spot in a waveform.
Mistake #2: Using a mux output as a clock or reset
Wrong: Switching between two clocks with a plain multiplexer
Right: Switch clocks with a glitch-free clock-mux cell, or change the select only while the output is held.
Why? In the AND-OR implementation, a select change with I0 = I1 = 1 can dip the output to 0 for a moment (a static-1 hazard), which a flip-flop sees as an extra clock edge.
Mistake #3: Leaving a select or data input undriven
Wrong: An unconnected select pin on a mux
Right: Drive every select and tie unused data inputs to a constant.
Why? A floating select shows up as x in simulation and as a random choice in silicon.
Practice Exercise
Challenge: Implement a Four-Variable Function With an 8-to-1 Mux
Implement F(A, B, C, D) = Σm(1, 3, 4, 11, 12, 13, 14, 15) with one 8-to-1 multiplexer and at most one inverter.
- Which variables drive the select lines S2 S1 S0?
- What do the eight data inputs connect to?
- Check A B C D = 1011 and 0100.
Hint
Use A, B, C as selects. Each pair of rows that differ only in D reduces to D, D', 0 or 1.
Solution
1. S2 S1 S0 = A B C. 2. Data inputs: I0 = D (A B C = 000: F = 0 when D = 0, 1 when D = 1) I1 = D (A B C = 001: F = 0 when D = 0, 1 when D = 1) I2 = D' (A B C = 010: F = 1 when D = 0, 0 when D = 1) I3 = 0 (A B C = 011: F = 0 when D = 0, 0 when D = 1) I4 = 0 (A B C = 100: F = 0 when D = 0, 0 when D = 1) I5 = D (A B C = 101: F = 0 when D = 0, 1 when D = 1) I6 = 1 (A B C = 110: F = 1 when D = 0, 1 when D = 1) I7 = 1 (A B C = 111: F = 1 when D = 0, 1 when D = 1) 3. A B C D = 1011: A B C = 101 selects I5 = 1, so F = 1 (m11 is in the list). A B C D = 0100: A B C = 010 selects I2 = D' with D = 0, so F = 1 (m4 is in the list).
Summary
In this tutorial, you learned:
- A multiplexer connects one of N data inputs to the output and needs log2 N select lines, with S0 the least significant
- Large muxes are trees of small ones; an N-to-1 mux costs N - 1 two-to-one muxes
- A 2n-to-1 mux implements any function of n + 1 variables by tying inputs to the last variable, its complement, 0 or 1
- A one-hot select needs no decoder: an AND-OR structure is smaller and faster than a mux tree
