The SR latch is the simplest memory element: two cross-coupled gates whose outputs hold each other in one of two stable states. A set input forces the output to 1, a reset input forces it to 0, and with both inactive the latch remembers. Adding an enable gives the gated latch and the D latch, the building blocks of edge-triggered flip-flops.
12 min read | Intermediate Level
What You'll Learn
- How a cross-coupled NOR or NAND pair stores one bit
- The set, reset, hold and forbidden states, and the active-low inputs of the NAND version
- How a gated SR latch and a D latch add an enable
Quick Answer: SR Latch Behaviour
| S | R | NOR latch Q | Action |
|---|---|---|---|
| 0 | 0 | Q (unchanged) | Hold |
| 1 | 0 | 1 | Set |
| 0 | 1 | 0 | Reset |
| 1 | 1 | Q = Q' = 0 | Forbidden: both outputs forced to 0 |
The NAND latch has active-low inputs S' and R': S' = 0 sets, R' = 0 resets, S' = R' = 1 holds, and S' = R' = 0 (forbidden) forces both outputs to 1.
How Two Gates Remember
Cross-couple two NOR gates, so that each gate's output feeds an input of the other. Q = NOR(R, Q') and Q' = NOR(S, Q). With S = R = 0 each gate acts as an inverter of the other, so the loop has two stable states: Q = 1, Q' = 0 and Q = 0, Q' = 1. The latch stays in whichever it was in.
- Set (S = 1): forces Q' to 0, which lets Q rise to 1. Removing S leaves Q = 1.
- Reset (R = 1): forces Q to 0, which lets Q' rise to 1. Removing R leaves Q = 0.
- Forbidden (S = R = 1): both outputs go to 0, so Q and Q' are no longer complements. If S and R return to 0 together, both gates race to 1 and the final state is unpredictable.
SR latch proportion rules both inputs inactive -> loop holds its state through feedback one input active -> forces one output, loop follows both inputs active -> both outputs forced to the same value (invalid) both released together -> state depends on which gate is faster
Where Is the SR Latch Used?
Contact debouncing is the classic use: a mechanical switch bounces for a few milliseconds, but an SR latch changes state on the first touch and ignores the bounces. Set/reset control flags and interrupt-pending bits also use the latch structure.
Debouncing a Switch With an SR Latch
A single-pole double-throw switch connects either S' or R' to ground (active low). When it moves from the R contact to the S contact, the contacts bounce. The latch output changes once:
| Event | S' | R' | Q |
|---|---|---|---|
| Switch rests on R contact | 1 | 0 | 0 |
| Leaves R contact (in flight) | 1 | 1 | 0 |
| Touches S contact | 0 | 1 | 1 |
| Bounces off S | 1 | 1 | 1 |
| Touches S again | 0 | 1 | 1 |
| Bounces off S | 1 | 1 | 1 |
| Settles on S | 0 | 1 | 1 |
Q goes to 1 on the first touch and stays there: each bounce returns the latch to its hold state (S' = R' = 1), not to reset.
Quick Check
Q: In a NAND SR latch, S' = 1 and R' = 0 are applied while Q = 1. What are Q and Q' afterwards?
Show Answer
R' = 0 resets the latch: Q = 0 and Q' = 1. Active-low inputs mean the 0 is the active level.
The Gated SR Latch and the D Latch
A gated SR latch adds an enable input C. Two input NAND gates pass S and R to the latch only while C = 1; with C = 0 the latch holds whatever the inputs do. A D latch removes the forbidden state by deriving R from S: S = D and R = D'.
| C | D | Q | Mode |
|---|---|---|---|
| 0 | X | Q (unchanged) | Hold |
| 1 | 0 | 0 | Transparent: Q follows D |
| 1 | 1 | 1 | Transparent: Q follows D |
While C = 1 the latch is transparent: any change on D passes to Q. This level sensitivity is why latches are not used where a signal must be sampled at one instant. Edge-triggered flip-flops are made of two latches in series (see D Flip-Flop).
Where Are D Latches Used?
Clock-gating cells hold the enable stable while the clock is high, and some high-speed designs use latch-based pipelines to borrow time between stages. Each flip-flop in a standard-cell library is itself two latches.
Quick Check
Q: A D latch has C = 1 and D goes 0, 1, 0 in turn. What does Q do, and what happens when C then falls?
Show Answer
Q follows D: 0, 1, 0, because the latch is transparent while C = 1. When C falls, Q holds the last value of D.
Common Mistakes
Mistake #1: Applying both inputs of a NOR latch at once
Wrong: S = R = 1, then releasing both together
Right: Never assert S and R together; add logic so that only one can be active.
Why? The outputs are both 0 while asserted, and the latch settles unpredictably when both are released at the same moment.
Mistake #2: Treating NAND latch inputs as active-high
Wrong: Driving S' = 1 to set a NAND latch
Right: Set with S' = 0 and reset with R' = 0; both inputs are 1 when idle.
Why? The NAND gate pulls its output to 1 only when an input is 0, so the active level is 0.
Mistake #3: Using a latch where a flip-flop is needed
Wrong: A transparent D latch in a loop that feeds its own input
Right: Use a flip-flop (two latches on opposite clock phases) for state that feeds back to itself.
Why? While the latch is transparent, the new value races around the loop, and the state can change more than once per clock.
Practice Exercise
Challenge: Trace a NOR SR Latch
A NOR SR latch starts with Q = 0. Apply the input pairs (S, R) in this order: (1,0), (0,0), (0,1), (0,0).
- Give Q after each step.
- Which step is the hold state, and what does Q do there?
- What is wrong with applying (1,1) next?
Hint
Set forces Q to 1, reset forces Q to 0, and (0,0) keeps the last value.
Solution
1. (1,0) set: Q = 1 (0,0) hold: Q = 1 (0,1) reset: Q = 0 (0,0) hold: Q = 0 2. Both (0,0) steps are hold states: Q keeps the value from the step before. 3. (1,1) forces Q = Q' = 0, and releasing both inputs together leaves the latch in an unpredictable state.
Summary
In this tutorial, you learned:
- Two cross-coupled NOR (or NAND) gates form an SR latch that holds one bit through feedback
- NOR latch: S = 1 sets, R = 1 resets, both 0 holds, both 1 is forbidden; the NAND latch has active-low inputs
- A gated latch adds an enable; a D latch (S = D, R = D') removes the forbidden state and is transparent while enabled
- A flip-flop is two latches on opposite clock phases, so it changes only at the clock edge
