A MOSFET (metal-oxide-semiconductor field-effect transistor) is a four-terminal, voltage-controlled switch. A voltage on the gate decides whether a thin conducting channel connects the source to the drain. Because the gate is separated from the channel by an insulating oxide, the gate draws no steady current - it controls the switch purely with an electric field.
12 min read | Beginner Level
What You'll Learn
- The role of the source, drain, gate, and body terminals
- Why the gate oxide makes the MOSFET a voltage-controlled device
- How channel width, length, and oxide thickness set a transistor's strength
- How NMOS and PMOS devices are built, and how each behaves as a switch
The Four Terminals
| Terminal | Symbol | Role |
|---|---|---|
| Source | S | Where carriers enter the channel. For NMOS, the lower-voltage end; for PMOS, the higher-voltage end. |
| Drain | D | Where carriers leave the channel. The other end of the switch. |
| Gate | G | The control input. Its voltage, relative to the source, turns the channel on or off. |
| Body (Bulk) | B | The silicon the transistor is built in. Usually tied to ground (NMOS) or VDD (PMOS) and often left off schematic symbols. |
A cross-section of an NMOS transistor shows how these terminals are arranged:
The source and drain are heavily doped n-type regions (n+), rich in free electrons. The body between them is p-type, so with no gate voltage there is no conducting path: the n+ regions are separated by p-type silicon, and current cannot flow. The gate's job is to create that path on demand.
The Gate Oxide: Why No DC Current Flows Into the Gate
The gate electrode sits on a very thin insulating layer, the gate oxide. The gate, oxide, and silicon underneath form a capacitor. Raising the gate voltage stores charge on this capacitor, and the matching charge in the silicon is what forms the channel.
Because the oxide is an insulator, the gate draws essentially no steady (DC) current. A gate only draws current while it is changing voltage, to charge or discharge its capacitance. This is why a CMOS logic gate's input looks like a small capacitor to whatever drives it.
Oxide thickness is one of the most powerful knobs in the whole device:
Oxide thickness proportion rules
thinner oxide -> larger gate capacitance per unit area
-> more channel charge for the same gate voltage
-> more current -> faster switching
thinner oxide -> electrons start tunnelling through the insulator
-> gate leakage current rises sharply
Plain silicon dioxide was thinned to roughly 1.2 nm - only a handful of atomic layers - before tunnelling leakage made it impractical. Modern processes use high-k dielectrics (hafnium-based materials) that behave like a thinner oxide electrically while staying physically thick enough to limit tunnelling. Process documents describe this with an equivalent oxide thickness (EOT), now around or below 1 nm.
Where Does Gate Capacitance Show Up?
In a standard-cell library, every cell's timing data lists its input pin capacitance. That value is mostly the gate capacitance of the transistors connected to the pin. Static timing analysis adds up the input capacitance of every cell on a net to find the load the driver must charge, which is why a net with high fanout gets slower.
The Channel: Width and Length
The channel is a very thin conducting layer - only a few nanometres deep - that forms in the silicon just under the gate oxide. Two dimensions control how much current it can carry:
| Dimension | Change | Effect on current | Analogy |
|---|---|---|---|
| Width (W) | ↑ Wider | ↑ Proportionally more current | More lanes on a road |
| Length (L) | ↑ Longer | ↓ Less current (roughly in proportion, for long channels) | A longer road to travel |
| Oxide thickness | ↓ Thinner | ↑ More current | A stronger grip by the gate |
Designers mostly work with the W/L ratio. Digital circuits almost always use the minimum length the process allows and vary the width to set strength. A cell labelled X2 or X4 in a standard-cell library is essentially the same circuit with transistors (or, in FinFET processes, fin counts) scaled up by about 2× or 4×.
Process names such as "5 nm" or "3 nm" are generation labels, not the physical gate length. Actual gate lengths in those processes are larger than the name suggests.
Quick Check
Q: If you double a transistor's width, what happens to its drive current and to the capacitance it presents to the gate that drives it?
Show Answer
Both roughly double. A wider transistor delivers about twice the current, but its gate area also doubles, so the stage driving it sees twice the load. Upsizing one transistor always makes the stage driving it work harder.
NMOS vs. PMOS Construction
CMOS technology uses two complementary transistor types built in opposite kinds of silicon:
| Property | NMOS | PMOS |
|---|---|---|
| Source/drain doping | n+ | p+ |
| Body | p-type substrate (or p-well) | n-well |
| Channel carriers | Electrons | Holes |
| Body connection | GND (lowest voltage) | VDD (highest voltage) |
| Source is the terminal at | Lower voltage | Higher voltage |
The source and drain are physically identical. Which one is the "source" is decided by the voltages at the moment: for an NMOS, the terminal at the lower voltage acts as the source. In a pass-transistor circuit, the two terminals can swap roles as signals change.
The body connections keep the junctions between the source/drain regions and the body reverse biased, so no current leaks into the body. The place-and-route tool inserts well-tap cells at regular intervals to make those connections.
The MOSFET as a Switch
For logic design, a MOSFET is modelled as an ideal switch between source and drain, controlled by the gate. This simple model is useful for understanding and for sketching transistor-level structures, and it shows exactly how the gate controls the path.
| Gate | NMOS | PMOS |
|---|---|---|
| 0 (low) | OFF: output disconnected (floating) | ON: output follows the data side |
| 1 (high) | ON: output follows the data side | OFF: output disconnected (floating) |
An OFF switch does not drive its output to 0: it simply leaves it disconnected, which is why transistors are always used in complementary pull-up and pull-down networks. In real chips the transistors live inside pre-designed standard cells, and designers work with gates and flip-flops, not individual transistors.
Where Is MOSFET Anatomy Changing?
Advanced processes no longer build flat (planar) transistors. In a FinFET, the channel is a thin vertical fin and the gate wraps around three sides of it. In gate-all-around (nanosheet) transistors, the gate surrounds stacked horizontal sheets completely. The terminals and their roles are unchanged; wrapping the gate around the channel simply gives it a much stronger grip, which reduces leakage in very short transistors.
Quick Check
Q: An NMOS transistor has one terminal at 0.9 V and the other at 0.3 V. Which terminal is the source?
Show Answer
The terminal at 0.3 V. For NMOS, the source is the lower-voltage terminal, because that is where electrons enter the channel. If the voltages reversed, the roles would swap.
Common Mistakes
Mistake #1: Assuming the gate draws current like a resistor load
The gate is insulated, so it draws no DC current. It draws current only while switching, to charge or discharge its capacitance. That is why CMOS power is dominated by switching activity and why fanout is described as capacitive load, not current load. Very thin oxides do leak a little through tunnelling, but that is a leakage effect, not normal gate operation.
Mistake #2: Treating source and drain as fixed pins
The MOSFET is physically symmetric. The source is simply the terminal where carriers enter, which is set by the voltages. Assuming a fixed direction leads to wrong analysis of pass transistors and transmission gates, where current can flow either way.
Mistake #3: Forgetting the body terminal
Three-terminal symbols hide the body, but it is always there and always connected. Its voltage affects when the transistor turns on, and a floating body can forward-bias junctions. In layout, missing well taps are a real sign-off failure.
Mistake #4: Expecting to draw custom transistors in a standard-cell design
In a typical digital flow the transistors are inside library cells that were designed and characterized in advance. The logic description does not create custom transistors; the synthesis tool chooses standard cells that implement the logic. Transistor-level design is reserved for the cell library itself and for special blocks such as memories.
Practice Exercise
Challenge: Size and Identify
- A PMOS transistor has one terminal at 0.8 V and the other at 0.5 V. Which is the source?
- An NMOS transistor with W = 200 nm and L = 20 nm delivers current I. Estimate the current if W is increased to 400 nm, and separately if L is increased to 40 nm (long-channel approximation).
- An NMOS pass switch has its gate driven by ENABLE. What does the output do when ENABLE = 0, and what level does it reach when it passes a logic 1?
Hint
For PMOS, carriers are holes, which enter from the higher-voltage side. Current scales with W and inversely with L.
Solution
1. The 0.8 V terminal is the PMOS source (higher voltage). 2. W 200 -> 400 nm : current ~2I (twice the width) L 20 -> 40 nm : current ~I/2 (twice the length) 3. ENABLE = 0: the NMOS is OFF and the output is disconnected (floating). ENABLE = 1: the output follows DATA. A 0 is passed completely, but a 1 only reaches about VDD - Vth, because an NMOS stops conducting when its gate-source voltage falls to the threshold.
Summary
In this tutorial, you learned:
- A MOSFET is a four-terminal, voltage-controlled switch: source, drain, gate, and body
- The gate is insulated by a thin oxide, so it draws no DC current and behaves like a capacitor
- Thinner oxide gives the gate more control and more current, until tunnelling leakage forces a switch to high-k dielectrics
- Current scales up with channel width and down with channel length
- NMOS uses n+ regions in a p-type body; PMOS uses p+ regions in an n-well
- Source and drain are set by voltage, not by construction
- For logic design a MOSFET is modelled as a switch; in real chips the transistors live inside pre-designed standard cells