The JK flip-flop extends the SR idea so that no input combination is forbidden: J sets, K resets, and J = K = 1 toggles the output. It is the most flexible of the classic flip-flops, and its excitation table has many don't-cares, which can make the next-state logic of a state machine smaller.
12 min read | Intermediate Level
What You'll Learn
- The JK characteristic table and equation Q+ = JQ' + K'Q
- How a JK flip-flop is built from a D flip-flop, and why it must be edge-triggered
- How to convert between JK, D and T flip-flops using the characteristic and excitation tables
- Why the don't-cares in the excitation table help when designing counters
Quick Answer: JK Flip-Flop
| J | K | Q after the clock edge | Action |
|---|---|---|---|
| 0 | 0 | Q | Hold |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Q' | Toggle |
Characteristic equation: Q(next) = J.Q' + K'.Q JK proportion rules J = K = 0 -> state unchanged J = K = 1 -> state inverted once per clock edge J and K -> sampled only at the active clock edge
Building a JK Flip-Flop
A JK flip-flop is an edge-triggered D flip-flop with logic that computes D from J, K and the present output: D = J.Q' + K'.Q. Working through the four cases shows why this is the JK function:
- J = 0, K = 0: D = Q, so the flip-flop holds
- J = 0, K = 1: D = 0, so it resets
- J = 1, K = 0: D = Q' + Q = 1, so it sets
- J = 1, K = 1: D = Q', so it toggles
Where Are JK Flip-Flops Used?
JK flip-flops appear in counters and in hand-designed controllers, where holding, setting, resetting and toggling are all useful operations. Many standard-cell libraries have no JK cell at all, so a JK is built from a D flip-flop and the gates above.
A single gated latch with J, K and the clock gated into it would be level-sensitive. With J = K = 1 it would keep toggling for as long as the clock is high, a problem called race-around. Edge-triggered or master-slave construction makes the flip-flop toggle exactly once per edge.
Tracing a JK Flip-Flop
| Clock edge | J | K | Q before | Q after | Action |
|---|---|---|---|---|---|
| 1 | 1 | 0 | 0 | 1 | Set |
| 2 | 0 | 0 | 1 | 1 | Hold |
| 3 | 1 | 1 | 1 | 0 | Toggle |
| 4 | 1 | 1 | 0 | 1 | Toggle |
| 5 | 0 | 1 | 1 | 0 | Reset |
| 6 | 1 | 1 | 0 | 1 | Toggle |
Quick Check
Q: A JK flip-flop has Q = 1 and J = 1, K = 1. What is Q after two clock edges?
Show Answer
The first edge toggles Q to 0, and the second toggles it back to 1, so Q = 1. With J = K = 1 the output has half the clock frequency.
Conversion and the Excitation Table
The excitation table answers the design question: given the transition wanted (present Q to next Q), which J and K are needed? An X means the input can be either value.
| Q | Q next | J | K |
|---|---|---|---|
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | X |
| 1 | 0 | X | 1 |
| 1 | 1 | X | 0 |
Two conversions follow directly from the characteristic equation:
- JK as a D flip-flop: J = D, K = D'. Then Q(next) = D.Q' + D.Q = D.
- JK as a T flip-flop: J = K = T. Then Q(next) = T.Q' + T'.Q = T xor Q, which is the T flip-flop (see T Flip-Flop).
Quick Check
Q: A JK flip-flop is wired with J = D and K = NOT D. With D = 0 and Q = 1, what is Q after the clock edge?
Show Answer
J = 0 and K = 1 reset the flip-flop, so Q = 0, which is the value of D. The connection J = D, K = D' makes the JK behave as a D flip-flop.
Where Does the JK Excitation Table Help?
Hand-designing a counter or a small state machine with JK flip-flops yields simpler input equations than D flip-flops, because every X in the excitation table is a free choice that a K-map can use to enlarge groups.
Common Mistakes
Mistake #1: Treating J = K = 1 as forbidden
Wrong: Avoiding J = K = 1 because the SR latch forbids S = R = 1
Right: Use J = K = 1 to toggle: it is the defining feature of the JK flip-flop.
Why? The feedback of Q and Q' into the input gates removes the forbidden state, so both inputs high simply inverts the output once per clock edge.
Mistake #2: Using a level-sensitive element with J = K = 1
Wrong: Holding J = K = 1 for a whole clock pulse on a gated JK latch
Right: Use an edge-triggered or master-slave JK flip-flop.
Why? A level-sensitive JK toggles again and again while the clock is high (race-around), so the final value is unpredictable.
Mistake #3: Swapping J and K
Wrong: Connecting K to the set condition
Right: J sets (J = 1, K = 0) and K resets (J = 0, K = 1).
Why? The two names are positions in the characteristic table; a swap inverts every set and reset in the design.
Practice Exercise
Challenge: A 2-Bit Counter From JK Flip-Flops
Design a 2-bit binary up counter Q1 Q0 (00, 01, 10, 11, 00, ...) with two JK flip-flops on the same clock.
- Which JK inputs does Q0 need?
- When must Q1 toggle, and which inputs does it need?
- Write the counting sequence for five clock edges starting from 00.
Hint
Q0 changes at every edge. Q1 changes only when Q0 is 1.
Solution
1. Q0 toggles on every clock edge: J0 = K0 = 1. 2. Q1 toggles when Q0 = 1 (the 01 -> 10 and 11 -> 00 transitions): J1 = K1 = Q0. 3. Clock edge Q1 Q0 before -> after 1 00 -> 01 2 01 -> 10 3 10 -> 11 4 11 -> 00 5 00 -> 01 (the sequence 00, 01, 10, 11, 00, 01 repeats every four edges)
Summary
In this tutorial, you learned:
- A JK flip-flop holds (0,0), resets (0,1), sets (1,0) and toggles (1,1); Q(next) = J.Q' + K'.Q
- It is an edge-triggered D flip-flop with D = J.Q' + K'.Q, so J = K = 1 toggles exactly once per edge
- The excitation table has don't-cares, and J = K = T gives a T flip-flop while J = D, K = D' gives a D flip-flop
- Level-sensitive JK elements suffer race-around; use an edge-triggered or master-slave construction
