Subthreshold Leakage & Short Channel Effects

A MOSFET that is OFF still conducts a small current. Below the threshold voltage, a few carriers have enough thermal energy to cross into the channel, producing subthreshold leakage. As transistors shrink, the drain starts to compete with the gate for control of the channel. These short-channel effects lower the threshold voltage and make that leakage worse. Across billions of transistors, leakage has become a major part of chip power.

14 min read | Intermediate Level

What You'll Learn

• Why current does not drop to zero below the threshold voltage
• How subthreshold swing links threshold voltage to OFF-state leakage
• What threshold roll-off and drain-induced barrier lowering (DIBL) are, and why they appear in short transistors
• How design and process techniques keep leakage under control

Quick Answer: Leakage Proportion Rules

Subthreshold leakage in proportions

  Below Vth, current falls by 10x for every "swing" S of gate voltage
    ideal limit at room temperature:  S = ~60 mV per 10x
    real transistors:                 S = ~70 to 100 mV per 10x

  Lower Vth by one swing (e.g. ~80 mV)   ->  OFF current ~10x higher
  Raise Vth by one swing                 ->  OFF current ~10x lower
  Hotter chip                            ->  Vth drops AND S worsens -> more leakage
  Shorter channel / higher V_DS          ->  Vth drops -> more leakage

Why an OFF Transistor Still Conducts

With the gate below Vth, there is no strong inversion channel, but the silicon under the gate is not completely empty of electrons either. The source is full of electrons, and an energy barrier keeps most of them from entering the channel region. The gate voltage sets the height of that barrier.

Electrons have a spread of thermal energies. A small fraction always have enough energy to get over the barrier. Once over, they diffuse to the drain and form a current. Because the fraction of electrons with enough energy falls off exponentially with barrier height, the current falls off exponentially as the gate voltage drops below Vth.

The subthreshold swing S is the gate voltage change needed to change this current by a factor of 10. At room temperature, the physics of thermal energy sets a limit of about 60 mV per decade. Real devices are worse because the gate does not have perfect control of the barrier: planar bulk transistors are typically around 80 to 100 mV per decade, while FinFETs, with a gate wrapped around the channel, come closer to 65-75 mV per decade.

Why Vth Cannot Simply Be Lowered

Subthreshold swing creates a hard trade-off. Lowering Vth adds overdrive and speed, but every swing's worth of Vth reduction multiplies OFF-state leakage by about 10.

This is why supply voltages stopped scaling down as fast as transistor dimensions. To keep performance, VDD must stay well above Vth, and Vth cannot drop much further without leakage exploding. Supplies in modern processes have settled at a few tenths of a volt to around one volt instead of continuing to fall.

Short-Channel Effects: The Drain Joins In

In a long transistor, the gate alone controls the barrier between source and channel. As the channel gets shorter, the source and drain regions sit so close together that the drain's electric field reaches into the channel region too. The gate now shares control with the drain, and it loses some of its grip.

DIBL is quoted in millivolts of Vth shift per volt of drain voltage. Well-controlled modern devices keep it to a few tens of mV/V; poorly controlled short planar devices can exceed 100 mV/V. An OFF transistor in a logic gate usually has the full supply across it, so DIBL applies directly to the leakage that matters most.

Why shrinking gets harder (cause and effect)

  shorter channel
    -> drain field reaches the source-side barrier
    -> gate has less control relative to the drain
    -> Vth drops (roll-off) and drops further at high V_DS (DIBL)
    -> OFF leakage rises
    -> designers must restore gate control:
         thinner / high-k gate dielectric
         shallower junctions and halo implants
         gate wrapped around the channel (FinFET, then gate-all-around)

Other Leakage Paths

Subthreshold current is usually the largest leakage component, but it is not the only one:

What This Means for Chip Design

An OFF transistor might leak only nanoamps or less, but a chip has billions of them, and every one of them is powered whenever its block is powered. Leakage has become a significant fraction of total power in advanced processes, and in devices that spend most of their time idle, such as phones and wearables, it often dominates standby power.

RTL does not describe leakage, and simulation does not show it. It is controlled during implementation:

Leakage-control toolbox (where each decision is made)

  Multi-Vt cells       synthesis / place-and-route swap HVT cells onto paths with slack
  Power gating         power intent file (UPF) defines switchable domains;
                       tools insert header/footer switch cells made from HVT devices
  Stacking             two OFF transistors in series leak far less than one,
                       because the middle node rises and reverse-biases the upper one
  Body biasing         reverse body bias raises Vth in idle modes (process-dependent)
  Lower temperature    leakage falls sharply with junction temperature

Cause-and-Effect Summary

Common Mistakes

1. HVT: Vth +100 mV -> leakage / 10^(100/80) = / ~17.8
        20 mW / 17.8 = ~1.1 mW
   LVT: Vth -80 mV  -> leakage x 10
        20 mW x 10  = 200 mW

2. 90% of the cells as HVT : 0.9 x 20 mW / 17.8 = ~1.0 mW
   10% of the cells as SVT : 0.1 x 20 mW        =  2.0 mW
   Total                                         = ~3.0 mW (about 6.7x lower)

3. Power gating: put the block in a switchable power domain and
   turn off its supply when idle. Only the high-Vt power switches
   (and any retention logic) keep leaking.