Moore Finite State Machines are predictable, glitch-free sequential circuits where outputs depend solely on the current state, not on inputs. This state-only dependency ensures synchronous, stable outputs that change only on clock edges, making Moore FSMs the preferred choice for control logic, traffic controllers, and systems requiring reliable, timing-critical operation.
Learning Objectives
- Understand how Moore FSMs generate outputs based solely on current state
- Differentiate Moore and Mealy FSMs in terms of output generation and timing characteristics
- Design Moore FSM state diagrams with outputs inside state circles
- Apply state encoding techniques (binary, Gray code, one-hot) to Moore FSM implementations
Reading time: 15 minutes | Difficulty: Advanced | Prerequisites: Finite State Machines, D Flip-Flop
Moore FSM Basics
Finite State Machines (FSMs) are fundamental building blocks in digital design, serving as the backbone for control logic in countless applications. Among the two primary types of FSMs, the Moore machine stands out for its predictable behavior and straightforward implementation. Understanding Moore FSMs is essential for anyone working in digital systems design, embedded systems, or hardware description languages.
A Moore Finite State Machine is a sequential circuit where outputs depend solely on the current state, not on the inputs. This characteristic distinguishes it from other FSM types and provides significant advantages in terms of timing and glitch-free operation. The machine transitions between states based on input conditions, but crucially, the output remains stable throughout the entire duration of each state.
The Moore FSM consists of three primary components: a state register that holds the current state, combinational logic that determines the next state based on current state and inputs, and output logic that generates outputs based solely on the current state. This architecture ensures that outputs change only on clock edges when state transitions occur, making Moore machines inherently synchronous and predictable.
Comparison with Mealy Machines
While both Moore and Mealy machines can implement the same functionality, they differ fundamentally in output generation:
Mealy machines produce outputs based on both the current state and current inputs, allowing them to react immediately to input changes. This can result in fewer states for equivalent functionality but introduces potential timing complexities.
Moore machines typically require more states than Mealy machines for the same task because outputs can only change with state transitions. However, this trade-off brings significant benefits:
- Glitch-free outputs: Moore outputs change only on clock edges
- Simpler timing analysis: Synchronous behavior throughout
- More robust design: Outputs not affected by input glitches
- Better for interfacing: Synchronous outputs ideal for connecting to other digital systems
The synchronous nature of Moore outputs makes them particularly suitable for interfacing with other synchronous systems and for applications where output stability is critical.
Example: Sequence Detector
Consider designing a Moore FSM that detects the sequence "101" in a serial bit stream. The machine needs four states: an initial idle state (S0), states after detecting "1" (S1), "10" (S2), and "101" (S3).
State behavior:
- In state S0 (output: 0), receiving a "1" moves to S1, while "0" stays in S0
- From S1 (output: 0), a "0" advances to S2, while another "1" remains in S1
- In S2 (output: 0), a "1" leads to S3, completing the sequence, while "0" returns to S0
- State S3 (output: 1) indicates sequence detection; a "0" transitions to S2 to begin searching for another sequence, while "1" goes to S1
This design ensures proper overlap handling, allowing detection of sequences like "110101" (detects "101" twice with overlap).
Common Beginner Mistakes
Mistake #1: Incomplete State Coverage
Wrong: Forgetting to specify transitions for all possible input combinations from every state.
Right: Every state must have defined transitions for all possible inputs, even if some transitions loop back to the same state.
Why: Undefined transitions lead to unpredictable behavior. The synthesized hardware will still do something when that input arrives—you need to specify what.
Mistake #2: Output Assignment Errors
Wrong: Making outputs depend on inputs rather than only on states (accidentally creating a Mealy machine).
Right: In Moore FSMs, outputs must depend solely on the current state, not on any inputs.
Why: Mixing Moore and Mealy characteristics violates the Moore machine definition and can cause timing issues, glitches, and incorrect synthesis.
Mistake #3: Insufficient States
Wrong: Trying to minimize states excessively, making the design impossible to implement correctly as a Moore machine.
Right: Use enough states to properly represent all distinct output conditions. Moore FSMs often need more states than Mealy FSMs.
Why: Since outputs depend only on states, each unique output condition may require a separate state. Trying to save states can make the design unimplementable or force you into a Mealy architecture.
Mistake #4: Reset State Not Properly Defined
Wrong: Neglecting to define a clear reset state and reset logic.
Right: Every FSM needs a well-defined reset state and proper reset logic (synchronous or asynchronous) to ensure predictable startup behavior.
Why: Without proper reset, the FSM may power up in an unknown or illegal state, causing unpredictable operation until it stumbles into a valid state.
Real-World Applications
Moore FSMs find extensive use across digital systems:
Traffic Light Controllers: Traffic light controllers use Moore FSMs for reliable, glitch-free light control. Each state (Red, Yellow, Green) has well-defined outputs (which lights are on), and transitions occur based on timers or sensors. The glitch-free nature of Moore outputs ensures no intermediate states where multiple contradictory lights might briefly turn on, which could cause accidents.
Communication Protocol State Management: Many communication protocols implement control logic using Moore FSMs. States like IDLE, SYNC, DATA, ACK, and ERROR each have specific output behaviors (control signals, status flags). The synchronous, predictable outputs simplify interfacing with other protocol layers and ensure timing requirements are met.
Additional Applications
- Vending machines: Transaction management with states for idle, accepting coins, dispensing product, returning change
- Elevator controllers: Floor sequencing and door control with states for each floor and door status
- Microprocessor design: Instruction decode and control units often employ Moore-style state machines for predictable timing
- Digital locks: Combination lock state machines with glitch-free unlock signals
Design Flow for Moore FSM
Designing a Moore FSM follows a systematic approach that ensures correctness and efficiency. The process begins with problem specification, where you clearly define the desired behavior, inputs, outputs, and any special conditions or constraints. Let's design a Moore FSM for a simple traffic light at a single intersection.
Step 1: Problem Specification
Objective: Design a traffic light controller that cycles through Green → Yellow → Red states.
Inputs:
- CLK: System clock
- RESET: Asynchronous reset (active high)
- TIMER_DONE: Signal indicating the current light duration has expired
Outputs:
- GREEN: Green light control (1 = ON, 0 = OFF)
- YELLOW: Yellow light control (1 = ON, 0 = OFF)
- RED: Red light control (1 = ON, 0 = OFF)
Behavior:
- Start in RED state after reset
- GREEN lights for a full timer cycle
- YELLOW lights for a full timer cycle
- RED lights for a full timer cycle
- Cycle repeats continuously
- Only one light should be ON at any time
- Transitions occur only when TIMER_DONE = 1
Special Conditions:
- RESET should immediately return to RED state
- System must be glitch-free (no intermediate states)
- All transitions must be synchronous with clock
Step 2: State Diagram Creation
Next comes state diagram creation. Identify all necessary states and draw circles representing each state with its associated output. Add directed arrows showing transitions between states, labeled with the input conditions that trigger each transition. Remember that in Moore machines, outputs are written inside the state circles, not on the transition arrows.
States Identified:
- S_RED: Red light is ON
- S_GREEN: Green light is ON
- S_YELLOW: Yellow light is ON
Transition Table
| Current State | TIMER_DONE | Next State |
|---|---|---|
| S_RED | 0 | S_RED |
| S_RED | 1 | S_GREEN |
| S_GREEN | 0 | S_GREEN |
| S_GREEN | 1 | S_YELLOW |
| S_YELLOW | 0 | S_YELLOW |
| S_YELLOW | 1 | S_RED |
Output Table
| State | RED | YELLOW | GREEN |
|---|---|---|---|
| S_RED | 1 | 0 | 0 |
| S_GREEN | 0 | 0 | 1 |
| S_YELLOW | 0 | 1 | 0 |
Notice how outputs are properties of states only, not transitions. This is the defining characteristic of Moore FSMs.
Step 3: State Encoding
The third step involves state encoding, where you assign binary codes to each state. Common encoding schemes include binary, Gray code, or one-hot encoding. The choice depends on factors like state count, transition patterns, and implementation technology. We have 3 states, so we need at least 2 bits to encode them.
Option A: Binary Encoding (Minimum Bits)
S_RED = 00 S_GREEN = 01 S_YELLOW = 10 (Unused) = 11
Advantages: Uses minimum number of flip-flops (2)
Disadvantages: Needs more complex combinational logic
Option B: One-Hot Encoding (Recommended for this design)
S_RED = 001 S_GREEN = 010 S_YELLOW = 100
Advantages:
- Simpler next-state logic
- Faster transitions (less combinational delay)
- Easier debugging (each flip-flop corresponds to one state)
- Better for FPGA implementations
Disadvantages: Uses more flip-flops (3 instead of 2)
Now let's assign state variable names:
Q2 Q1 Q0 = state bits Q0 = 1 when in S_RED Q1 = 1 when in S_GREEN Q2 = 1 when in S_YELLOW
Step 4: Next-State Logic Development
Following this, you develop the next-state logic using Karnaugh maps, Boolean algebra, or automated synthesis tools to derive equations for the next state based on current state and inputs. Given below is the truth table for next-state logic.
| Q2 | Q1 | Q0 | TIMER_DONE | Q2_next | Q1_next | Q0_next |
|---|---|---|---|---|---|---|
| 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 |
Step 5: Output Logic Development
For Moore machines, outputs depend ONLY on current state. With one-hot encoding, each state bit directly corresponds to one output! This is a major advantage of one-hot encoding for Moore machines.
RED = Q0 GREEN = Q1 YELLOW = Q2
Shown below is the truth table for outputs:
| Q2 | Q1 | Q0 | RED | YELLOW | GREEN |
|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 0 | 1 | 0 |
Step 6: Implementation and Testing
Finally, implement the design using hardware description languages like Verilog or VHDL, or through schematic capture, followed by thorough simulation and verification.
Quick Check
Question: Why does the "101" sequence detector need 4 states as a Moore FSM, but would only need 3 states as a Mealy FSM?
Answer: Moore needs a dedicated state for the output condition
Moore FSM (4 states):
- S0: No progress (output: 0)
- S1: Detected "1" (output: 0)
- S2: Detected "10" (output: 0)
- S3: Detected "101" (output: 1) ← Dedicated output state
Mealy FSM (3 states):
- S0: No progress
- S1: Detected "1"
- S2: Detected "10"
- On input=1 from S2: outputs 1 (completing "101") and transitions to S1 for overlap — no separate output-only state needed
Key insight: In Moore FSMs, outputs are state properties. To generate output=1, we need a state where output=1. In Mealy FSMs, outputs are transition properties, so we can generate output=1 during a transition without needing a separate state. This is why Moore FSMs typically require more states than equivalent Mealy FSMs.
Summary
- Moore FSMs generate outputs based solely on the current state, not on inputs, ensuring glitch-free, synchronous operation.
- Outputs in Moore FSMs change only on clock edges during state transitions, providing predictable timing.
- Moore FSMs typically require more states than Mealy FSMs for equivalent functionality (1-2 more states).
- State diagrams show outputs inside state circles, not on transition arrows like Mealy FSMs.
- One-hot encoding often simplifies Moore FSM output logic, as each flip-flop can directly drive an output.
- Moore FSMs are ideal for control logic, traffic controllers, and systems requiring stable, glitch-free outputs.
- Every Moore FSM must have a well-defined reset state to ensure predictable startup and recovery from errors.
