A demultiplexer (demux) is the mirror image of a multiplexer: one data input, several outputs, and a select code that decides which output receives the input. Unselected outputs stay at 0. It steers a single write-enable to one register out of many and splits a shared line back into separate channels. A demultiplexer is also a decoder with its enable input used as the data input.
11 min read | Intermediate Level
What You'll Learn
- How 1-to-2 and 1-to-4 demultiplexers work and what unselected outputs do
- Why a demultiplexer is a decoder with the data on the enable input
- How a multiplexer and demultiplexer pair share one line in time-division multiplexing
- How a demultiplexer steers one write-enable to a single register
Quick Answer: Demultiplexer vs. Decoder
| Decoder with enable | Demultiplexer | |
|---|---|---|
| Code / select inputs | Code inputs | Select inputs |
| Extra input | Enable E | Data input A |
| Selected output | 1 when E = 1 | Follows A |
| Other outputs | 0 | 0 |
| Data input tied to 1 | Decoder | Becomes a decoder |
The 1-to-2 and 1-to-4 Demultiplexer
A 1-to-2 demux has a data input A, a select S and two outputs. The selected output copies A, and the other is 0:
| S | A | Y0 | Y1 |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 |
Y0 = S'.A Y1 = S.A
A 1-to-4 demux uses two select lines S1 S0, and each output is a 3-input AND of the data and one combination of the select literals:
Y0 = S1'.S0'.A Y1 = S1'.S0 .A Y2 = S1 .S0'.A Y3 = S1 .S0 .A
The unselected outputs are driven to 0. A demultiplexer has no memory: when the select changes, the previously active output returns to 0 at once.
Demultiplexer proportion rules select changes -> old output drops to 0, new output follows A data input A = 0 -> every output is 0, whatever the select one more select line -> twice as many outputs and AND gates
A Demultiplexer Is a Decoder With the Data on Enable
The equations above are the decoder-with-enable equations with E replaced by A: Dk = E . (minterm k of the code). Use the enable as the data input and the decoder becomes a demultiplexer. Tie the data input to 1 and a demultiplexer is a plain decoder. This is why parts such as the 74x138 are sold as "3-to-8 decoder / demultiplexer". See Digital Decoder Circuit.
Quick Check
Q: A 1-to-4 demultiplexer has S1 S0 = 10 and A = 1. Which output is 1, and what are the others?
Show Answer
Y2 = 1, because S1 S0 = 10 selects output 2 and it follows A. Y0, Y1 and Y3 are 0.
Sharing One Line: Time-Division Multiplexing
A multiplexer and demultiplexer with a common select let several signals share one wire. A counter steps through the select codes: the mux puts channel k on the wire in time slot k, and the demux delivers it to output k.
| Time slot | S1 S0 | Channel sent | Value on the wire | Demux output |
|---|---|---|---|---|
| 0 | 00 | A0 | 5 | B0 = 5 |
| 1 | 01 | A1 | 9 | B1 = 9 |
| 2 | 10 | A2 | 3 | B2 = 3 |
| 3 | 11 | A3 | 12 | B3 = 12 |
| 4 | 00 | A0 | 5 | B0 = 5 |
| 5 | 01 | A1 | 9 | B1 = 9 |
| 6 | 10 | A2 | 3 | B2 = 3 |
| 7 | 11 | A3 | 12 | B3 = 12 |
Both selects must carry the same value in every slot, or every channel lands on the wrong output. Each receiver output normally feeds a register that holds the value between slots, because the demux outputs return to 0.
Where Is Time-Division Sharing Used?
Multi-channel data converters send several sampled channels over one serial link, and telephone-style links interleave many calls on one wire. A shared select from a counter or a frame-sync signal keeps sender and receiver in step.
Steering a Write Enable
The most common demultiplexer in a design is hidden: the logic that turns one write-enable and an address into one enable per register. Only the addressed register sees its enable go high, so only that register loads the data on the clock edge.
A demultiplexer maps to the same AND gates as a decoder, one per output, with shared inverters on the select lines. Each output drives the load enable of a register (an enable multiplexer in front of each flip-flop, or a clock-gating cell).
Quick Check
Q: A register file has four registers and a 1-to-4 write-enable demux. With WE = 1 and write address 10, which enables are 1, and which registers change on the next clock edge?
Show Answer
Only enable 2 is 1, so only register 2 loads the write data. Registers 0, 1 and 3 keep their values because their enables are 0.
Where Is Write-Enable Steering Used?
Register files, memory-mapped peripheral registers and FIFO storage arrays all steer one write strobe to a single entry selected by an address. A memory row decoder is a demultiplexer whose data input is the word-line enable.
Common Mistakes
Mistake #1: Expecting a demultiplexer to hold its value
Wrong: Reading Y0 after the select has moved to Y1 and expecting the old data
Right: Capture each output in a register that uses the demux output as its enable.
Why? A demultiplexer has no memory: the old output returns to 0 as soon as the select changes.
Mistake #2: Using a demux output as a clock
Wrong: Connecting a demux output to the clock pin of a register
Right: Use one clock for every register and the demux output as its load enable.
Why? Decoded signals glitch and skew against the main clock, which creates false or late clock edges.
Mistake #3: Mismatched selects in a mux and demux pair
Wrong: Deriving the sender and receiver selects from separate counters
Right: Drive both from the same counter or synchronize them explicitly.
Why? If the selects differ by even one slot, every channel is delivered to the wrong output.
Practice Exercise
Challenge: Steer a Write Enable to Eight Registers
A register file has eight 16-bit registers selected by a 3-bit write address, and one write-enable signal WE.
- How many 1-to-2 demultiplexers would a tree need, and how many AND gates does a flat 1-to-8 demux need?
- Write the equation for enable 5.
- For WE = 1 and write address 101, which enable is active?
Hint
A tree of 1-to-2 demuxes needs 1 + 2 + 4 of them. A flat version needs one AND gate per output.
Solution
1. Tree of 1-to-2 demuxes: 1 + 2 + 4 = 7 (N - 1 for N outputs). Flat version: eight 4-input ANDs (WE and three select literals) plus 3 inverters for the select complements. 2. EN5 = WE . A2 . A1' . A0 (register 5 loads when WE = 1 and the address A2 A1 A0 = 101) 3. 101 = 5, so only enable 5 is 1: register 5 loads and the other seven keep their values.
Summary
In this tutorial, you learned:
- A demultiplexer routes one input to the selected output; all other outputs are 0
- A demultiplexer is a decoder with the data on the enable input, and a decoder is a demultiplexer with the data tied to 1
- A multiplexer and demultiplexer with a common select share one wire in time-division multiplexing
- Use demux outputs as load enables, never as clocks
