The D flip-flop is the standard storage element of synchronous design. On each active clock edge it captures the value on its D input and holds it at Q until the next edge. Everything between edges is ignored, which is what makes timing analysis possible. Registers, counters, state machines and pipelines are all built from D flip-flops.
13 min read | Intermediate Level
What You'll Learn
- How a master-slave pair of latches makes an edge-triggered flip-flop
- The characteristic equation Q+ = D, and the setup, hold and clock-to-Q timing parameters
- How synchronous and asynchronous resets and enables change the circuit
Quick Answer: D Flip-Flop
| D | CLK | Q after the edge | Action |
|---|---|---|---|
| 0 | rising edge | 0 | Capture 0 |
| 1 | rising edge | 1 | Capture 1 |
| X | no edge | Q (unchanged) | Hold |
Characteristic equation: Q(next) = D D flip-flop proportion rules clock edge arrives -> Q takes the value D had just before the edge D changes between edges -> no effect on Q D unstable near the edge -> setup/hold violation, Q may be metastable
How an Edge-Triggered Flip-Flop Is Built
A single D latch is transparent while its enable is high, so on its own it cannot capture a value at one instant. A flip-flop uses two D latches in series, a master and a slave, enabled on opposite clock phases:
- While CLK = 0, the master is transparent and follows D; the slave is closed and holds Q
- At the rising edge the master closes, keeping the value D had at that instant, and the slave opens
- While CLK = 1, the slave passes the master's stored value to Q; the master ignores D
Where Are D Flip-Flops Used?
A register is a row of D flip-flops sharing one clock, so a 64-bit register uses 64 of them. Pipeline registers, the program counter, configuration registers and every state bit of a state machine are D flip-flops.
Tracing a D Flip-Flop
Q after each rising edge equals D just before it. Changes of D between edges, such as the short pulse before edge 3, are ignored:
| Rising edge | D just before the edge | Q after the edge | Note |
|---|---|---|---|
| 1 | 1 | 1 | |
| 2 | 1 | 1 | |
| 3 | 0 | 0 | D pulses high and falls again between edges 2 and 3 |
| 4 | 1 | 1 | |
| 5 | 0 | 0 | |
| 6 | 0 | 0 |
Quick Check
Q: D = 1 for the whole interval before a rising edge, then D falls to 0 just after the edge. What does Q show after the edge?
Show Answer
Q = 1. The flip-flop captured the value D had at the edge; the later fall of D is ignored until the next edge.
Timing: Setup, Hold and Clock-to-Q
| Parameter | Meaning | Example value |
|---|---|---|
| Setup time (tsu) | D must be stable this long before the clock edge | 20 ps |
| Hold time (th) | D must stay stable this long after the clock edge | 5 ps |
| Clock-to-Q (tcq) | Delay from the clock edge until Q is valid | 40 ps |
If D changes inside the window set by tsu and th, the master latch may settle at an intermediate voltage (metastability). Timing analysis makes sure this never happens inside one clock domain (see Propagation Delay & Critical Path). Signals from another clock domain need a synchronizer (see Synchronizers & Clock Domain Crossing).
Quick Check
Q: A design has a 1 ns clock period, tcq = 40 ps and tsu = 20 ps. How much time is left for combinational logic between two flip-flops (ignoring skew)?
Show Answer
1000 - 40 - 20 = 940 ps. The clock period must cover clock-to-Q, the logic delay and the setup time.
Reset and Enable
| Feature | Hardware |
|---|---|
| Synchronous reset | Acts only at a clock edge: an AND gate on D, or a library flop with a synchronous reset pin |
| Asynchronous reset | Acts at once, without a clock: a dedicated reset pin on the flop, with no extra data-path logic |
| Enable | A 2-to-1 multiplexer in front of D that recirculates Q, or an enable flop / clock-gating cell |
An asynchronous reset costs no data-path logic but needs care when it is released (see Synchronizers & Clock Domain Crossing). A synchronous reset is part of the logic and is covered by normal timing analysis.
Where Does Reset Style Matter?
Control flip-flops that must reach a safe state before the clock runs use asynchronous reset, while wide datapath registers often use no reset at all, since the data is overwritten before it is used. Fewer reset pins mean smaller flops and less routing.
Common Mistakes
Mistake #1: Violating setup or hold time
Wrong: Changing D less than tsu before or th after the clock edge
Right: Keep D stable around the edge by meeting the clock period and hold constraints.
Why? The master latch can settle at an intermediate voltage, so Q may be wrong or take extra time to resolve.
Mistake #2: Expecting a synchronous reset to work without a clock
Wrong: Relying on a synchronous reset while the clock is stopped
Right: Use an asynchronous reset, or keep the clock running during reset.
Why? A synchronous reset takes effect only at a clock edge, so a stopped clock never resets the flop.
Mistake #3: Expecting Q to follow D
Wrong: Reading Q right after D changes and expecting the new value
Right: Q updates only at the active clock edge, so the new D appears at Q one edge later.
Why? A flip-flop ignores D between edges. That is the difference from a latch.
Practice Exercise
Challenge: Trace a Flip-Flop With Asynchronous Reset
A D flip-flop with an active-low asynchronous reset RSTN starts at Q = 0. At six rising edges, D = 1, 0, 1, 1, 0, 1. RSTN is 0 (asserted) during edges 3 and 4 and 1 otherwise.
- Give Q after each edge.
- How would the result differ if the reset were synchronous and RSTN were asserted only between edges 2 and 3 (released before edge 3)?
Hint
While RSTN = 0 the flip-flop is held at 0 whatever D and the clock do.
Solution
1. Edge D RSTN Q after 1 1 1 1 2 0 1 0 3 1 0 0 4 1 0 0 5 0 1 0 6 1 1 1 2. A synchronous reset acts only at a clock edge. A pulse that ends before edge 3 is never seen by the flip-flop, so Q follows D at edge 3 (Q = 1). An asynchronous reset would have cleared Q as soon as RSTN dropped.
Summary
In this tutorial, you learned:
- A D flip-flop captures D at the active clock edge and holds it: Q(next) = D
- It is built from two latches (master and slave) on opposite clock phases, so Q changes only at the edge
- D must be stable for the setup time before and the hold time after the edge, or the flip-flop can go metastable
- An asynchronous reset acts at once through a dedicated pin; a synchronous reset acts only at the clock edge; an enable adds a feedback multiplexer
