AOI and OAI Complex Gates

A complex CMOS gate implements a whole inverted sum-of-products or product-of-sums in a single stage. An AND-OR-INVERT (AOI) gate computes NOT((A AND B) OR C); an OR-AND-INVERT (OAI) gate computes NOT((A OR B) AND C). They are built with the same rule as NAND and NOR: the pull-down network implements the function, and the pull-up network is its structural dual. The result uses fewer transistors and less delay than a cascade of simple gates.

14 min read | Intermediate Level

What You'll Learn

• How to build any inverting function as one CMOS stage using series and parallel networks
• How to derive the pull-up network as the dual of the pull-down
• Why AOI and OAI cells save transistors, delay, and power
• How common functions map to AOI/OAI cells in a standard-cell netlist, and where they are used

The Recipe: Pull-Down First, Then the Dual

Building a single-stage CMOS gate for  Y = NOT( F )

  1. Write F using only AND and OR of the inputs (no inversions inside F)
  2. Pull-down network (NMOS), between Y and GND:
       AND  -> transistors in SERIES
       OR   -> transistors in PARALLEL
  3. Pull-up network (PMOS), between VDD and Y:
       the DUAL: every series becomes parallel, every parallel becomes series
  4. Check: for every input combination exactly one network conducts

  Example: Y = NOT( (A AND B) OR C )     -> AOI21
     pull-down: (NA series NB) in parallel with NC
     pull-up:   (PA parallel PB) in series with PC

Check the dual for one case: A = 1, B = 1, C = 0. In the pull-down, NA and NB are both ON, so the series branch conducts and Y is pulled LOW. In the pull-up, PA and PB are both OFF, so the parallel pair blocks the path to VDD even though PC is ON. Exactly one network conducts, as required.

The digits in the name give the size of each group: AOI21 has one 2-input AND group and one single input; AOI22 has two 2-input AND groups.

Why One Complex Gate Beats Several Simple Ones

Fewer transistors means less area and less switched capacitance, so less dynamic power. Fewer stages usually means less delay. There is a cost: stacked transistors must be widened, so a complex gate's inputs present more capacitance than an inverter's. With the usual sizing, the stacked A and B inputs of an AOI21 have a logical effort of 2 and the C input 5/3, compared with 4/3 for a NAND2. As long as stacks stay short, the saving in stages outweighs this.

Checking the AOI21 on Every Input

The truth table of the AOI21 shows that exactly one network conducts for each of the eight input combinations. That is the property that makes a static CMOS gate: no direct path from VDD to ground, and an output that is never left floating.

How Functions Map to Complex Cells

Synthesis tools recognize inverted sum-of-products and product-of-sums patterns and map them to complex cells:

Non-inverted versions such as (A·B) + C often come out as an AOI21 followed by an inverter (some libraries call that an AO21 cell), or the tool pushes the inversion into the next stage and uses the AOI directly. This is why synthesized netlists are full of AOI and OAI cells even though designers rarely write inverted sum-of-products explicitly.

Limits: How Complex Can a Gate Get?

Any inverting function can in principle be built as one stage, but tall stacks become slow:

Stack height trade-off

  more inputs in series  ->  each transistor must be wider
                         ->  more input capacitance, more internal node capacitance
                         ->  slower, especially for the input farthest from the output

  practical limit: about 3-4 transistors in series in either network
  beyond that: split into two stages (e.g. AOI + NAND)

Within a stack, input order matters too. The input connected to the transistor nearest the output switches fastest, because the internal nodes below it are already charged or discharged. Libraries document which pin is fastest, and timing tools route the latest-arriving signal to it when they can swap logically equivalent pins.

Common Mistakes

1. Pull-down: (NA || NB) in series with (NC || ND)
   Pull-up:   (PA series PB) in parallel with (PC series PD)

2. OAI22: 8 transistors, one stage
   OR2 = NOR2 + inverter = 6 transistors each
   2 x OR2 + NAND2 = 6 + 6 + 4 = 16 transistors, 3 stages

3. A = 1, B = 0, C = 1, D = 0: (A + B) = 1 and (C + D) = 1, so the series
   pair of parallel groups conducts and the pull-down pulls Y low.
   In the pull-up, PA is OFF (A = 1), so the series path PA-PB is open;
   PC is OFF (C = 1), so PC-PD is open too. Exactly one network conducts.