A p-n junction forms wherever p-type and n-type silicon meet. Carriers near the boundary cancel each other out, leaving a thin depletion region with no free carriers and a built-in electric field. Applying a voltage one way shrinks that region and lets current flow; applying it the other way widens it and blocks current. This one-way behaviour is a diode, and every MOSFET contains p-n junctions at its source and drain.
14 min read | Intermediate Level
What You'll Learn
- How the depletion region and built-in field form when p-type meets n-type
- What forward bias and reverse bias do to the depletion region and the current
- How doping and voltage set the depletion width and junction capacitance
- Where p-n junctions hide inside every CMOS standard cell
Quick Answer: Forward vs. Reverse Bias
| Bias | Connection | Depletion region | Current |
|---|---|---|---|
| Zero bias | No external voltage | Natural width (equilibrium) | None (net) |
| Forward bias | + on p-side, - on n-side | Shrinks | Flows once voltage exceeds ~0.6-0.7 V, then rises steeply |
| Reverse bias | + on n-side, - on p-side | Widens | Blocked, apart from a tiny leakage current |
What Happens When P-Type Meets N-Type?
Imagine joining a block of p-type silicon (full of holes) to a block of n-type silicon (full of free electrons). Right at the boundary, each side has a huge surplus of a carrier the other side lacks.
Carriers naturally spread from where they are crowded to where they are scarce, just as a drop of ink spreads through water. This spreading is called diffusion:
- Electrons diffuse from the n-side into the p-side.
- Holes diffuse from the p-side into the n-side.
- When an electron meets a hole, the electron fills the missing bond and both disappear as free carriers. This is called recombination.
- Electrons diffuse from the n-side into the p-side, and holes diffuse from the p-side into the n-side.
- Carriers meet and recombine near the boundary, so free carriers vanish there.
- Fixed dopant ions are left uncovered: positive donor ions on the n-side edge, negative acceptor ions on the p-side edge.
- These exposed ions create an electric field pointing from the n-side to the p-side.
- The field pushes electrons back to the n-side and holes back to the p-side.
- When the field's push balances the diffusion push, the junction is in equilibrium and no net current flows.
The Depletion Region: An Insulating Gap Inside Silicon
The zone around the boundary that has lost its free carriers is the depletion region. With no free carriers, it behaves like an insulator sandwiched between two conducting regions.
It is not empty of charge, though. It is full of fixed charge: positive donor ions on the n-side and negative acceptor ions on the p-side. Those ions cannot move, but together they produce an electric field across the region. The voltage associated with this field is the built-in potential, typically about 0.6 to 1.0 V for silicon junctions. Heavier doping on either side gives a higher built-in potential.
How wide is the depletion region? Typically a fraction of a micrometre, and its width follows two proportion rules:
Depletion width proportion rules
heavier doping -> more fixed ions per unit length
-> less width needed to build the field
-> NARROWER depletion region
unequal doping -> depletion extends mostly into the LIGHTLY doped side
(e.g. n+ source into p-body: almost all of the
depletion region sits in the p-body)
more reverse bias -> WIDER depletion region
Quick Check
Q: If an unbiased junction has a built-in potential of 0.7 V, can you connect a voltmeter across it and read 0.7 V?
Show Answer
No. Where the metal leads contact the silicon, additional contact potentials form that exactly cancel the built-in potential. A junction at equilibrium delivers no energy, so a voltmeter reads zero. The built-in potential is real inside the silicon but cannot be used as a battery.
Forward Bias: Shrinking the Gap
Connect the positive terminal to the p-side and the negative terminal to the n-side. The applied voltage opposes the built-in field, so the barrier holding carriers back gets lower and the depletion region gets narrower.
Below roughly 0.5 V, very little happens. At about 0.6 to 0.7 V for a silicon junction - still below the full built-in potential - the barrier is lowered enough that carriers pour across in large numbers and current rises very steeply.
Forward-bias proportion rule (silicon junction, room temperature) every +60 mV of forward voltage -> roughly 10x more current 0.50 V -> I 0.56 V -> 10 x I 0.62 V -> 100 x I 0.68 V -> 1,000 x I Takeaway: a forward-biased diode behaves almost like a switch that "turns on" near 0.6-0.7 V.
Reverse Bias: Widening the Gap
Connect the positive terminal to the n-side and the negative terminal to the p-side. Now the applied voltage adds to the built-in field. Free carriers are pulled further away from the boundary, more fixed ions are exposed, and the depletion region widens.
The majority carriers now face a taller barrier and essentially stop crossing. A tiny reverse leakage current remains. It comes from minority carriers and from electron-hole pairs generated by heat inside the depletion region, which the field immediately sweeps across. This current is small, grows only slowly with reverse voltage, and is very sensitive to temperature.
If the reverse voltage is made very large, current eventually rises sharply. This is breakdown. In most junctions it happens by avalanche: carriers accelerated by the strong field knock electrons out of bonds, and those new carriers knock out more. In very heavily doped junctions, electrons can instead tunnel straight through the thin depletion region (Zener breakdown). Normal digital circuits operate far below the breakdown voltage.
| Increase this | Depletion width | Current | Junction capacitance |
|---|---|---|---|
| Forward voltage | ↓ Narrower | ↑ Rises steeply (~10× per 60 mV) | ↑ Larger |
| Reverse voltage | ↑ Wider | Tiny leakage, almost constant | ↓ Smaller |
| Doping on either side | ↓ Narrower | - | ↑ Larger |
| Temperature | Slightly narrower | ↑ Leakage rises quickly | - |
The Junction as a Capacitor
A reverse-biased junction is two conducting regions separated by an insulating layer - which is exactly the structure of a capacitor. The depletion region is the "dielectric", and its width acts like the plate spacing:
- Wider depletion region → plates further apart → less capacitance
- Narrower depletion region → plates closer together → more capacitance
Every transistor source and drain is a junction with the body, so every one of them adds this diffusion (junction) capacitance to the node it drives. It is part of the load a logic gate must charge and discharge, which makes it part of every gate's delay and dynamic power.
Where Are p-n Junctions in a CMOS Chip?
An NMOS transistor has n+ source and drain regions sitting in a p-type body, so it contains two p-n junctions. A PMOS transistor has p+ regions in an n-well, plus the n-well itself forms a junction with the p-type substrate. For the chip to work, all of these junctions must stay reverse biased at all times. That is why the p-substrate is tied to ground and the n-well is tied to VDD - the lowest and highest voltages on the chip.
What Comes Out of Synthesis?
You never write a diode in RTL, and logic synthesis never produces one from your Verilog. Junctions still appear in the final layout in three ways:
- Parasitic junctions inside every transistor, contributing leakage and capacitance to every standard cell.
- Well-tap cells inserted by the place-and-route tool at regular intervals. They connect the n-well to VDD and the substrate to ground so that the parasitic junctions stay reverse biased.
- Antenna diodes inserted by the router. During manufacturing, long metal wires can collect charge that would damage a thin gate oxide. A small reverse-biased diode on that net gives the charge a safe path to the substrate.
Where Are Deliberate Diodes Used?
Every I/O pad on a chip has protection diodes to VDD and ground. During normal operation they are reverse biased and invisible. When an electrostatic discharge hits a pin, they forward bias and steer the current away from the delicate internal transistors. Many SoCs also use the forward voltage of an on-chip p-n junction (a diode or a diode-connected transistor) as a temperature sensor, since that voltage falls by about 2 mV for every degree Celsius of warming.
Quick Check
Q: A drain node sits at VDD while the NMOS body is at 0 V. If VDD is raised, does the drain junction capacitance go up or down?
Show Answer
Down. The drain-to-body junction is reverse biased by VDD. A higher reverse voltage widens the depletion region, which increases the effective plate spacing and reduces the capacitance.
Common Mistakes
Mistake #1: Describing the depletion region as having no charge
The depletion region has no free (mobile) carriers, but it is full of fixed ionised dopant atoms. That fixed charge is what creates the built-in field. Saying it is "neutral" or "empty" makes it impossible to explain why a field exists there.
Mistake #2: Assuming a forward-biased diode conducts at any positive voltage
A silicon junction carries negligible current until the forward voltage approaches about 0.6 V. Below that, the barrier is only slightly lowered. This threshold-like behaviour is why a small voltage difference between a well and its tie point is usually harmless, while a few hundred millivolts more is not.
Mistake #3: Treating reverse current as exactly zero
Reverse-biased junctions always leak a small current driven by thermally generated carriers. For one junction it is tiny, but a chip has billions of them, and the leakage grows rapidly with temperature. Junction leakage is one component of a chip's standby power.
Mistake #4: Leaving a well or substrate without a solid connection
If the n-well is not firmly tied to VDD, or the substrate to ground, noise or injected current can shift their voltage. A shift of around 0.6 V is enough to forward-bias a source or drain junction, injecting current into the body. In the worst case this triggers latch-up, a self-sustaining short from VDD to ground through parasitic structures. Missing or too-sparse well taps are a real sign-off failure, not just a layout nit.
Practice Exercise
Challenge: Diagnose a Floating Body
An NMOS transistor has its source at 0 V and its drain at 1.0 V. Because a well tap was missed, its p-type body is not tied to ground, and substrate noise pushes the body up to +0.8 V.
- For the source-to-body junction and the drain-to-body junction, state whether each is forward or reverse biased.
- What current flows as a result, and why is it a problem?
Hint
The body is the p-side and the source and drain are the n-sides. A junction is forward biased when the p-side is more positive than the n-side.
Solution
Source-to-body: p-side (body) = 0.8 V, n-side (source) = 0 V
p is 0.8 V above n -> FORWARD biased (above ~0.6 V)
Drain-to-body: p-side (body) = 0.8 V, n-side (drain) = 1.0 V
n is 0.2 V above p -> REVERSE biased (normal)
Result: the source junction conducts strongly, injecting electrons
into the body. This wastes current, disturbs neighbouring devices,
and can trigger latch-up. Correct well-tap placement keeps the body
at 0 V so every junction stays reverse biased.
Summary
In this tutorial, you learned:
- At a p-n boundary, carriers diffuse across and recombine, leaving a depletion region with no free carriers
- Exposed fixed ions in the depletion region create a built-in field that stops further diffusion
- Forward bias shrinks the depletion region; current rises steeply above about 0.6-0.7 V, roughly 10× per 60 mV
- Reverse bias widens the depletion region and blocks current, apart from a small temperature-sensitive leakage
- Heavier doping narrows the depletion region; more reverse bias widens it and lowers junction capacitance
- Every MOSFET contains p-n junctions that must stay reverse biased, which is why well taps exist
