NMOS and PMOS transistors are mirror images. An NMOS conducts with electrons and turns ON when its gate is high; a PMOS conducts with holes and turns ON when its gate is low. Each one is good at passing only one logic level cleanly, and holes move more slowly than electrons. Those two facts decide how every CMOS gate is wired and sized.
14 min read | Intermediate Level
What You'll Learn
- How NMOS and PMOS turn-on conditions mirror each other
- Why NMOS passes a strong 0 but a weak 1, and PMOS the reverse
- Why PMOS devices are traditionally drawn wider, and how that is changing
- How an inverter and a transmission gate are built from the two transistor types
Quick Answer: Side-by-Side Comparison
| Property | NMOS | PMOS |
|---|---|---|
| Channel carrier | Electrons | Holes |
| Turns ON when | Gate is above source by more than Vth (gate HIGH) | Gate is below source by more than |Vth| (gate LOW) |
| Source normally connected to | GND side | VDD side |
| Passes a strong | 0 | 1 |
| Passes a weak | 1 (reaches only about VDD - Vth) | 0 (reaches only about |Vth|) |
| Carrier mobility in silicon | Higher (about 2.5-3× holes) | Lower |
| Role in static CMOS | Pull-down network | Pull-up network |
Mirror-Image Turn-On Conditions
For an NMOS, a positive gate-to-source voltage pulls electrons to the surface and forms the channel. More gate voltage means more channel charge and more current.
For a PMOS, everything flips. The body is n-type, the channel carriers are holes, and the gate must go below the source to attract them. In a CMOS gate the PMOS source is at VDD, so "gate low" means "gate near 0 V", which gives the largest source-to-gate voltage and the strongest channel.
Turn-on rules (VDD = 0.8 V, |Vth| = 0.3 V, source at the usual rail)
NMOS (source = 0 V):
gate = 0.8 V -> V_GS = 0.8 V > 0.3 V -> ON (overdrive 0.5 V)
gate = 0.0 V -> V_GS = 0.0 V < 0.3 V -> OFF
PMOS (source = 0.8 V):
gate = 0.0 V -> V_SG = 0.8 V > 0.3 V -> ON (overdrive 0.5 V)
gate = 0.8 V -> V_SG = 0.0 V < 0.3 V -> OFF
Because one type is ON exactly when the other is OFF, a PMOS and an NMOS sharing the same gate signal form a complementary pair. That pairing is where the "C" in CMOS comes from.
Strong and Weak Logic Levels
A transistor passes a signal only while it stays ON. Consider an NMOS with its gate at VDD trying to pass a 1 from one side to the other:
NMOS passing a 1 (gate = VDD, input = VDD)
output starts at 0 V_GS = VDD - 0 -> strongly ON, output rises
output rises V_GS = VDD - output -> overdrive shrinks
output = VDD - Vth V_GS = Vth -> channel barely exists
-> output stalls near VDD - Vth
NMOS passing a 0: the source stays at 0 V, V_GS stays at VDD,
so the NMOS stays fully ON and the output reaches 0 V exactly.
As the output rises, it becomes the NMOS source, so the gate-to-source voltage shrinks until the transistor turns itself off one threshold below VDD. The body effect raises Vth further as the source rises, making the drop even larger. PMOS has the mirror problem: it passes a full 1 but can only pull down to about |Vth| above ground.
This is the reason static CMOS gates always use PMOS in the pull-up network (connected to VDD) and NMOS in the pull-down network (connected to GND). Each transistor type only ever passes the level it passes well, so outputs reach full rail-to-rail swing.
Where Are Transmission Gates Used?
When a signal must pass through a switch in both logic states, designers put an NMOS and a PMOS in parallel, driven by opposite control signals. This transmission gate passes a strong 0 through the NMOS and a strong 1 through the PMOS. Transmission gates appear inside many standard-cell flip-flops, latches, and multiplexers, where they give a compact, full-swing switch.
Quick Check
Q: VDD = 0.9 V and NMOS Vth = 0.35 V. An NMOS pass transistor with its gate at VDD passes a logic 1. Roughly what voltage appears at the output?
Show Answer
About 0.9 - 0.35 = 0.55 V, and somewhat lower in practice because the body effect raises Vth as the output rises. A gate receiving this weak 1 may not switch cleanly and may draw extra leakage current.
Why PMOS Is Drawn Wider
In silicon, holes move roughly 2.5 to 3 times more slowly than electrons. With the same size and the same overdrive, a PMOS delivers substantially less current than an NMOS. For a gate to have matched rise and fall times, its pull-up PMOS must be made wider to compensate.
Sizing rule for matched rise/fall (classic planar CMOS) hole mobility ~ 1/2 to 1/3 of electron mobility -> PMOS width ~ 2x to 3x NMOS width for equal drive Common textbook choice for an inverter: W_p : W_n = 2 : 1 (a compromise between matched delay and the extra area and input capacitance that a wider PMOS adds)
This asymmetry is smaller in advanced processes. Strain engineering and silicon-germanium PMOS channels have boosted hole mobility substantially, and in FinFET processes transistor width comes in whole fins. Many modern cells use equal or nearly equal fin counts for PMOS and NMOS. The underlying physics has not changed; the process has been tuned to close the gap.
Where Does NMOS/PMOS Asymmetry Show Up in Layout?
Standard cells are drawn in rows with a VDD rail on one edge and a VSS rail on the other. The PMOS transistors sit in a continuous n-well along the VDD side, and the NMOS transistors sit along the VSS side. In planar libraries the PMOS region is often visibly taller to hold the wider devices. Adjacent cells share the n-well and the power rails, which is what lets thousands of cells butt together in one row.
An Inverter and a Transmission Gate
A CMOS inverter is one PMOS from VDD to the output and one NMOS from the output to GND, with both gates tied to the input. Think of each transistor as a switch that is closed when its turn-on condition is met:
| Input | PMOS (to VDD) | NMOS (to GND) | Output |
|---|---|---|---|
| 0 | ON (passes VDD) | OFF | 1 |
| 1 | OFF | ON (passes GND) | 0 |
Exactly one switch is closed, so the output is always driven to a full level and almost no current flows in steady state.
A transmission gate puts an NMOS and a PMOS in parallel between a data input D and an output, with opposite gate signals: the NMOS gate is the enable EN and the PMOS gate is its complement, so an extra inverter makes EN-bar. Each transistor covers the other's weakness, the NMOS passes a strong 0 and the PMOS a strong 1:
| EN | NMOS half | PMOS half | Output |
|---|---|---|---|
| 0 | OFF | OFF | Disconnected (high impedance, floating) |
| 1 | ON | ON | Follows D, with a full 0 or a full 1 |
Real gates are built from these pieces already, inside the library cell's layout. You do not draw individual transistors when designing logic with standard cells; this view explains why the cells behave the way they do and how pass-gate cells such as multiplexers and XOR gates are made.
Quick Check
Q: In the inverter above, why is the PMOS connected to VDD and the NMOS to GND, and not the other way round?
Show Answer
A PMOS passes a strong 1 and an NMOS passes a strong 0. Swapping them would make the output reach only VDD - Vth for a 1 and |Vth| for a 0. In the real circuit the swapped version would not even invert: input 1 would turn on the NMOS and pull the output up to a weak 1, and input 0 would turn on the PMOS and pull it down to a weak 0. The result is a weak, non-inverting buffer.
Common Mistakes
Mistake #1: Thinking a PMOS turns on whenever its gate is at 0 V
A PMOS turns on when its gate is sufficiently below its source. In a standard gate the source is at VDD, so a 0 V gate turns it on. If the PMOS source is at a lower voltage, as inside a stack or a pass-transistor path, a 0 V gate gives much less overdrive, or none at all.
Mistake #2: Using an NMOS to pull an output up to VDD
An NMOS can only pull its output up to about VDD - Vth, and the body effect makes this worse. The weak high level eats into noise margin and can leave the next gate's PMOS partly ON, causing static current. Pull-ups belong to PMOS.
Mistake #3: Assuming equal-size NMOS and PMOS give equal rise and fall times
In planar CMOS, an equal-width PMOS is roughly 2 to 3 times weaker, so the rising edge is noticeably slower than the falling edge. Check the library's rise and fall delays rather than assuming symmetry; the balance depends on the process and the cell's sizing.
Mistake #4: Trusting an ideal-switch model to show a weak 1
A simplified switch model treats an NMOS as an ideal switch that passes a full logic 1. It does not model the threshold drop. A pass-transistor circuit that looks correct in such a model can still fail in silicon because the real output only reaches VDD - Vth. Use circuit-level (SPICE) simulation for pass-transistor designs.
Practice Exercise
Challenge: Build a 2:1 Multiplexer From Transmission Gates
Using two transmission gates and one inverter, build a 2:1 multiplexer with data inputs A and B, select SEL and output Y, where Y = A when SEL = 0 and Y = B when SEL = 1. Then explain why a transmission gate is used instead of a single NMOS per input.
Hint
Each input needs its own transmission gate. One gate should be enabled by SEL, the other by its inverse.
Solution
Gate A: transmission gate between A and Y
NMOS gate = SEL-bar, PMOS gate = SEL -> ON when SEL = 0
Gate B: transmission gate between B and Y
NMOS gate = SEL, PMOS gate = SEL-bar -> ON when SEL = 1
One inverter generates SEL-bar from SEL.
Only one gate is ON at a time, so Y is driven by exactly one input.
A single NMOS per input would pass a 0 cleanly but only a degraded 1 of about VDD - Vth. The parallel PMOS in each transmission gate passes the 1 at full VDD, so the output swings rail to rail for both data values.
Summary
In this tutorial, you learned:
- NMOS turns ON with its gate high relative to its source; PMOS turns ON with its gate low relative to its source
- NMOS passes a strong 0 and a weak 1; PMOS passes a strong 1 and a weak 0
- Static CMOS uses PMOS pull-up networks and NMOS pull-down networks to get full-swing outputs
- Transmission gates combine both types to pass either level cleanly
- Lower hole mobility traditionally makes PMOS about 2× wider, though modern processes have narrowed the gap
- Ideal-switch models do not show threshold drops, so pass-transistor circuits need circuit-level simulation
