T Flip-Flop

The T (toggle) flip-flop has one control input: with T = 0 it holds its state, and with T = 1 it inverts its output at every clock edge. Tie T high and the output toggles at half the clock frequency, a divide-by-2. Chains of T flip-flops are the classic binary counters, in two flavours: a ripple (asynchronous) counter and a synchronous counter.

12 min read | Intermediate Level

What You'll Learn

• The T flip-flop characteristic equation Q+ = T xor Q and how to build it from a D flip-flop
• How a T flip-flop divides the clock by two
• How ripple and synchronous binary counters are built, and how their delays differ
• Why chips use synchronous counters rather than ripple counters

Quick Answer: T Flip-Flop

Characteristic equation:   Q(next) = T xor Q
T flip-flop proportion rules
  T = 1                      ->  Q toggles at every clock edge
  Q toggles every edge       ->  Q has half the clock frequency
  n toggle stages in a chain ->  clock divided by 2^n

Building a T Flip-Flop

A T flip-flop is a D flip-flop with an XOR gate in front of D: D = T xor Q. With T = 0 the XOR passes Q back (hold), and with T = 1 it passes Q' (toggle). It is also a JK flip-flop with J = K = T (see JK Flip-Flop).

Ripple (Asynchronous) Counters

Use falling-edge-triggered T flip-flops with T = 1 and connect the Q output of each one to the clock input of the next: a stage toggles when the stage before it falls, and the chain counts clock pulses in binary. (With rising-edge flip-flops the next stage is clocked from the inverted output instead, because feeding Q straight in would count down.) Each stage divides by two, so the outputs form the count:

Ripple counter delay proportions
  each stage is clocked by the previous stage's output
  the count settles after  n x t_cq  (worst case, all bits change)
  illustrative t_cq = 40 ps:  3 bits -> 120 ps,  8 bits -> 320 ps
  while it settles, decoded outputs can show wrong intermediate counts

A ripple counter is small, but the stages do not change together: when the count goes 0111 to 1000 the outputs pass through intermediate values 0110, 0100 and 0000 before 1000. Logic that decodes a count from such a counter can glitch.

Synchronous Counters

A synchronous counter clocks every flip-flop with the same clock, so all bits change together after one clock-to-Q delay. Bit i must toggle when all lower bits are 1, so its T input is the AND of the lower bits:

3-bit synchronous up counter
  T0 = 1
  T1 = Q0
  T2 = Q0 . Q1

The price is the AND gates, and the AND chain also limits the maximum clock rate for wide counters: the T input of the top bit must settle before the next edge.

Ripple counters use derived clocks, which complicate clock-tree design and timing analysis. A synchronous counter is three D flip-flops with an incrementer in front of them (see Half-Adder), and that is the style used for counters in chips.

Common Mistakes

1. A down counter borrows instead of carrying: bit i toggles when all lower
   bits are 0.
2. T0 = 1
   T1 = Q0'
   T2 = Q0' . Q1'
3. From 000: T0 = 1, T1 = 1, T2 = 1, so every bit toggles -> 111.
   From 111: T0 = 1, T1 = 0, T2 = 0, so only Q0 toggles -> 110.
   From 110: T0 = 1, T1 = 1, T2 = 0 -> 101, and so on down to 000.