Current in silicon is carried by two kinds of carriers - electrons and holes - moving by two mechanisms: drift and diffusion. Temperature changes both how many carriers exist and how easily they move. The result is that a hotter chip leaks far more current, and its transistors switch at a different speed. Understanding this is the first step toward understanding leakage power and why chips are signed off across temperature corners.
13 min read | Intermediate Level
What You'll Learn
- How electrons and holes both contribute to current, through drift and diffusion
- Why higher temperature produces more carriers and more leakage
- Why higher temperature also slows carriers down, and how the two effects compete
- How temperature shows up in chip power budgets and timing sign-off
Current Is Moving Charge - of Both Signs
Current is the rate at which charge crosses a point. In a metal, only electrons move. In silicon, both electrons and holes move, and both contribute.
Under an applied voltage, electrons drift toward the positive terminal and holes drift toward the negative terminal. They move in opposite directions, but because they carry opposite charges, their contributions to current add together rather than cancel.
In doped silicon, the majority carrier usually dominates. In an NMOS channel, current is almost entirely electrons; in a PMOS channel, almost entirely holes.
Two Ways Carriers Move: Drift and Diffusion
| Mechanism | What drives it | Proportion rule | Where it dominates |
|---|---|---|---|
| Drift | An electric field pushes carriers | More field or more carriers → more current | A strongly ON transistor channel, resistors, wires |
| Diffusion | Carriers spread from crowded to sparse regions | Steeper difference in carrier crowding → more current | Forward-biased junctions, and a transistor that is nominally OFF |
How easily a carrier drifts is called its mobility. In silicon, electrons have roughly 2.5 to 3 times the mobility of holes. With the same field and the same number of carriers, electron current is about three times larger. That is the physical reason PMOS transistors are drawn wider than NMOS transistors.
Where Does Carrier Mobility Matter?
Because hole mobility limits PMOS strength, many advanced processes deliberately stretch or compress the silicon lattice under the transistor channel, or add germanium to the PMOS channel, to make carriers move faster. These "strain engineering" techniques raise drive current without shrinking the transistor, and they are standard in high-performance CPU and GPU processes.
Temperature Effect #1: More Carriers
Heat gives electrons more random energy. More of them gain enough to jump the band gap, creating extra electron-hole pairs. In silicon near room temperature, the number of thermally generated carriers roughly doubles every 8 to 12 °C, with the doubling interval stretching slightly as the chip gets hotter.
In a doped region, the majority carrier count is set by the dopants and barely changes. The minority carriers and thermally generated carriers are the ones that surge - and those are exactly the carriers responsible for leakage.
Temperature -> leakage, cause and effect
temperature up
-> more electrons gain enough energy to cross the band gap
-> more thermally generated carriers and minority carriers
-> more reverse current through every p-n junction
-> more current through transistors that are supposed to be OFF
-> more static (leakage) power
How fast does leakage grow?
exponentially with temperature - roughly doubling every 10 to 25 degC
junction leakage: toward the fast end (tracks carrier generation)
subthreshold leakage: usually slower (process and Vt flavour dependent)
The largest leakage path in a modern transistor is subthreshold leakage: current that trickles through the channel even when the transistor is OFF. It has the same root cause - a small fraction of carriers have enough thermal energy to get over an energy barrier - and it is covered in detail in the MOSFET lessons.
Quick Check
Q: In n-type silicon doped at 1017 per cm3, does the electron count change much between 25 °C and 85 °C? Does the hole count?
Show Answer
The electron (majority) count stays close to 1017 because it is fixed by the dopant atoms. The hole (minority) count rises by more than a thousand times over that range. Thermally generated pairs grow very quickly with temperature, and the minority count grows even faster than the thermally generated count does. That is why leakage, which depends on minority carriers, is so temperature-sensitive.
Temperature Effect #2: Slower Carriers
Heat also makes the silicon lattice vibrate more strongly. Moving carriers collide with those vibrations more often, so they drift more slowly. Mobility falls as temperature rises.
For a transistor that is strongly ON, the carrier count in the channel is set by the gate voltage, not by temperature. Lower mobility then means less drive current and slower switching. So heat has two opposite effects:
| Effect of higher temperature | Impact on OFF transistors | Impact on ON transistors |
|---|---|---|
| More thermally generated carriers | ↑ Leakage rises sharply | Small effect |
| Lower mobility | Small effect | ↓ Drive current falls, gates get slower |
| Lower turn-on voltage of the transistor | ↑ Leakage rises further | ↑ Helps drive current, most noticeable at low supply voltage |
At normal supply voltages, the mobility effect usually wins: hot chips are slower. At very low supply voltages, the turn-on voltage effect can win instead, so the chip is slower when cold. This reversal is called temperature inversion, and it is why timing sign-off in advanced nodes checks both temperature extremes.
Example sign-off corner list (process_voltage_temperature)
corner ss_0p72v_125c -> slow devices, low V, hot : setup check
corner ss_0p72v_m40c -> slow devices, low V, cold : setup check
(catches temperature inversion)
corner ff_0p88v_m40c -> fast devices, high V, cold : hold check
corner ff_0p88v_125c -> fast devices, high V, hot : leakage power
Where Does Temperature Dependence Show Up?
Smartphone and laptop processors carry on-die temperature sensors and reduce their clock frequency and voltage when they get hot, a behaviour known as thermal throttling. One reason is that leakage power climbs steeply with temperature, eating into the battery and the cooling budget. In standby, when almost nothing switches, leakage is often the dominant drain on the battery.
The Feedback Loop: Thermal Runaway
Leakage produces heat, and heat produces more leakage. Under normal conditions, the package and heat sink remove heat fast enough to reach a stable temperature. If cooling is inadequate or leakage is unusually high, the loop can feed itself:
The loop is stable as long as the cooling system removes heat at least as fast as the extra leakage adds it. If leakage grows faster than cooling can keep up, temperature keeps climbing until the chip throttles, shuts down, or is damaged.
This is one reason chip power budgets are calculated at the hottest expected junction temperature, not at room temperature.
Where Is Leakage Budgeted?
Data-centre accelerators and server processors are specified with a maximum junction temperature, typically somewhere in the 90 to 125 °C range. Power analysis runs the design at that temperature, because leakage at the hot corner can be ten or more times larger than at room temperature. Automotive chips are qualified up to even higher temperatures, which makes leakage control a first-order design goal for them.
Common Mistakes
Mistake #1: Assuming only electrons carry current in silicon
Holes carry current too, and in p-type regions and PMOS channels they are the main carrier. Electron and hole currents add, even though the particles move in opposite directions.
Mistake #2: Assuming the hottest corner is always the slowest
At normal supply voltages, a hot chip is usually slower. At low supply voltages, temperature inversion can make the cold corner slower instead. Signing off setup timing only at the hot corner can miss real failures in low-voltage designs.
Mistake #3: Thinking clock gating removes leakage
Clock gating stops switching, which removes dynamic power. The gated transistors are still powered, so they still leak, and that leakage still rises with temperature. Removing leakage from an idle block requires cutting its supply with power gating.
Mistake #4: Quoting leakage at room temperature
A leakage number measured or simulated at 25 °C can be ten or more times lower than the same design at 110 °C. Power budgets, battery-life estimates, and thermal designs must use the leakage at the expected operating temperature.
Practice Exercise
Challenge: Estimate Leakage Across Temperature
A block leaks 10 mW at 25 °C. Assume a planning rule that leakage doubles for every 15 °C rise, and estimate its leakage at:
- 55 °C (a phone in a pocket)
- 85 °C (a busy laptop processor)
- 115 °C (a hot-corner sign-off temperature)
Then explain why the chip's dynamic power does not follow the same curve.
Hint
Count how many 15 °C steps sit between 25 °C and each target, then double once per step.
Solution
55 degC: (55 - 25) / 15 = 2 steps -> 10 mW x 2^2 = 40 mW 85 degC: (85 - 25) / 15 = 4 steps -> 10 mW x 2^4 = 160 mW 115 degC: (115 - 25) / 15 = 6 steps -> 10 mW x 2^6 = 640 mW
Dynamic power comes from charging and discharging capacitance each time a node switches. It depends on capacitance, supply voltage, and switching frequency, none of which depend strongly on carrier generation across the band gap. Leakage, by contrast, is driven directly by thermally energetic carriers, so it grows exponentially with temperature. The real rate varies by process, so treat these as order-of-magnitude estimates.
Summary
In this tutorial, you learned:
- Electrons and holes both carry current; they move in opposite directions but their currents add
- Drift is carrier motion driven by a field; diffusion is motion from crowded to sparse regions
- Electrons are about 3× more mobile than holes, which sets NMOS/PMOS sizing
- Higher temperature generates far more carriers, so leakage rises exponentially - doubling every 10 to 25 °C depending on process and mechanism
- Higher temperature also lowers mobility, so strongly ON transistors usually get slower
- At low supply voltages, temperature inversion can make the cold corner the slowest
- Power budgets and timing sign-off must be checked across the full temperature range
Proportion takeaway: More dopant → more carriers → more conductivity. More reverse bias → wider depletion region → more blocking. Temperature is a hidden dial that raises carrier count for free, which makes leakage a central concern in deep sub-micron CMOS.
