A CMOS NOR gate is the mirror image of a NAND: its NMOS transistors are in parallel and its PMOS transistors are in series. The output is pulled HIGH only when every series PMOS is ON - when all inputs are LOW - and any input going HIGH turns on an NMOS that pulls the output LOW. Because it stacks the slower PMOS devices, NOR is larger and slower than NAND for the same drive, so it is used where its logic fits rather than as a default.
11 min read | Intermediate Level
What You'll Learn
- How parallel NMOS and series PMOS implement the NOR function
- Why the series PMOS stack makes NOR slow and area-hungry
- How NOR and NAND relate through De Morgan's theorem
- When NOR is still the right choice, and how NOR cells appear in netlists
The NOR2 Circuit
- Pull-down (parallel NMOS): either NA or NB can connect Y to GND. If A = 1 or B = 1, Y is LOW.
- Pull-up (series PMOS): current can reach Y from VDD only through PA and PB. Both must be ON, so Y is HIGH only when A = 0 and B = 0.
| A | B | PA | PB | NA | NB | Y |
|---|---|---|---|---|---|---|
| 0 | 0 | ON | ON | OFF | OFF | 1 |
| 0 | 1 | ON | OFF | OFF | ON | 0 |
| 1 | 0 | OFF | ON | ON | OFF | 0 |
| 1 | 1 | OFF | OFF | ON | ON | 0 |
The networks are duals again: the parallel pull-down implements A OR B, the series pull-up implements (NOT A) AND (NOT B), and those two conditions are exact complements by De Morgan's theorem.
De Morgan links NAND and NOR structures
NOR: Y = NOT (A OR B) = (NOT A) AND (NOT B)
pull-down: A, B in parallel pull-up: PMOS in series
NAND: Y = NOT (A AND B) = (NOT A) OR (NOT B)
pull-down: A, B in series pull-up: PMOS in parallel
Swap series <-> parallel and NMOS <-> PMOS to go from one to the other.
The Internal Node
Between the two series PMOS there is a node that exists only inside the gate, call it p1: PA connects VDD to p1, and PB connects p1 to Y. When A is 1, PA is OFF, so p1 is cut off from VDD and the pull-up path is open, whatever B is. That is why a single input at 1 is enough to stop the output from being pulled high. As in the NAND, the capacitance of this internal node is one more thing to charge, which adds to the delay of the stack.
Why the Series PMOS Stack Hurts
Two effects combine against NOR:
- PMOS devices are already the weaker transistor type, because holes move more slowly than electrons.
- Putting them in series doubles the resistance, so each must be widened again to compensate.
Sizing a NOR2 to match a reference inverter (NMOS width 1, PMOS width 2)
pull-up: 2 PMOS in series
each needs half the resistance -> width 4 each
pull-down: 2 NMOS in parallel
worst case one ON -> width 1 each
input capacitance per input = NMOS 1 + PMOS 4 = 5
logical effort = 5 / 3 = ~1.67 (NAND2: 4/3 = ~1.33)
NOR3: PMOS width 6 each -> input cap 7 -> logical effort 7/3 = ~2.33
NOR4: PMOS width 8 each -> input cap 9 -> logical effort 3
The wide series PMOS devices also take up area and add capacitance at the internal node between them. Every extra input makes the problem worse, which is why NOR gates with more than three inputs are uncommon in standard-cell libraries.
Quick Check
Q: In a NOR2, which output edge is the weak one if the PMOS devices are not widened, and why?
Show Answer
The rising edge. A rising output needs both series PMOS ON, and two slow PMOS in series have roughly twice the resistance of one. The falling edge can use either parallel NMOS, which is already the faster device type.
What Maps to What
| Function | Cell | Transistors |
|---|---|---|
| Y = NOT(A + B) | One NOR2 cell | 4 |
| Y = NOT A · NOT B (the same function by De Morgan) | Also one NOR2 cell, not two inverters and an AND | 4 instead of 10 |
| Y = A + B | OR2 cell: internally a NOR2 followed by an inverter | 6 |
Synthesis recognizes NOT A · NOT B and NOT(A + B) as the same function; it does not build separate inverters and an AND. Whether a NOR2 or another structure is chosen depends on timing: on a critical path, a tool may restructure logic to use NAND-based cells instead, pushing inversions onto signals where they are cheaper.
When NOR Is Still the Right Choice
NOR is slower for the same drive, but it is not wrong. It is used wherever the logic naturally needs "none of these inputs is active":
Where Are NOR Gates Used?
Zero-detect logic in ALUs and comparators asks whether all bits of a result are 0, which is exactly a NOR - built as a tree of NOR and NAND stages for wide buses. Cross-coupled NOR pairs form the classic SR latch used in some set/reset control logic. Memory row decoders also use NOR-style logic, often in dynamic circuit styles where the slow series PMOS problem does not arise.
Where Does NOR's Weakness Show Up?
On timing-critical paths in high-frequency designs, optimization tools tend to replace NOR-heavy structures with NAND or AOI cells and adjust inversions elsewhere. Reviewing a critical path report and seeing a NOR3 or NOR4 with a large delay is a common prompt to restructure the logic or pick a different cell.
Common Mistakes
Mistake #1: Assuming NOR and NAND of the same size are equally fast
NOR stacks the slow PMOS devices, so for the same drive it needs much wider PMOS and presents more input capacitance: logical effort 5/3 versus 4/3 for two inputs, and the gap grows with more inputs.
Mistake #2: Getting the series and parallel networks backwards
In a NOR, the NMOS are in parallel and the PMOS in series. Drawing the NAND structure and labelling it NOR produces a circuit whose output is wrong for two of the four input combinations. Check every design with the rule: series pull-down means AND, parallel pull-down means OR, then invert.
Mistake #3: Writing inverted-input AND and expecting extra inverters
NOT A · NOT B does not need two inverters and an AND gate. By De Morgan's theorem it is the NOR function, and a single NOR2 cell (or a better equivalent) implements it. Write the logic for readability and let the synthesis tool find the structure.
Mistake #4: Using wide NOR gates on critical paths
A NOR4 has four PMOS in series, each roughly four times wider than an inverter's PMOS. Its rising edge is slow and its input capacitance is high. Split wide NOR functions into a tree, for example two NOR2s feeding a NAND2.
Practice Exercise
Challenge: Zero Detect on a 4-bit Bus
You need ZERO = 1 when the 4-bit bus D3 D2 D1 D0 is all zeros.
- Write the Boolean expression for ZERO.
- Show a two-level implementation using only NOR2 and AND2-type logic that avoids a NOR4, and explain why it is better.
Hint
Each NOR2 tells you whether a pair of bits is all zero. Both pairs must be all zero.
Solution
1. ZERO = NOT (D3 + D2 + D1 + D0) (a 4-input NOR: 1 only if every bit is 0) 2. Z_LO = NOT (D1 + D0) NOR2: lower pair is zero Z_HI = NOT (D3 + D2) NOR2: upper pair is zero ZERO = Z_LO . Z_HI both pairs zero In cells: 2 x NOR2 + 1 AND2 (or NAND2 + inverter).
A NOR4 would stack four PMOS in series, each about 4x wider than an inverter PMOS, giving a slow rising edge and heavy input loading. The tree uses only two-high stacks. Synthesis tools make this choice automatically from the 4-input NOR.
Summary
In this tutorial, you learned:
- A CMOS NOR has parallel NMOS in the pull-down and series PMOS in the pull-up
- NOR and NAND are structural duals, linked by De Morgan's theorem
- Series PMOS stacks force very wide transistors, giving NOR2 a logical effort of 5/3
- NOR gets worse faster than NAND as inputs are added, so wide NORs are split into trees
- NOT(A + B) and NOT A · NOT B are the same function, a single NOR2, which tools may restructure on critical paths
- NOR remains useful for zero detection, SR latches, and some decoder styles