A decoder turns a binary code into a single active line: give it a 3-bit number and exactly one of eight outputs goes high. Inside, it is a set of AND gates, one per input combination, so every output is a minterm of the inputs. That makes a decoder the standard way to select one memory chip, register or peripheral from an address, and a general-purpose building block for logic.
13 min read | Intermediate Level
What You'll Learn
- How an n-to-2n decoder works and why its outputs are minterms
- How enable inputs let you build a larger decoder from smaller ones
- How to implement a Boolean function with a decoder and an OR gate
- How large decoders are split into predecoded stages
Quick Answer: Decoder Sizes
| Decoder | Code inputs | Outputs | Gates | Inverters |
|---|---|---|---|---|
| 2-to-4 | 2 | 4 | 4 AND gates, 3 inputs each (with enable) | 2 |
| 3-to-8 | 3 | 8 | 8 AND gates, 4 inputs each (with enable) | 3 |
| 4-to-16 | 4 | 16 | 16 AND gates, 5 inputs each (with enable) | 4 |
Decoder proportion rules one more code input -> twice as many outputs and AND gates one more code input -> every AND gate gets one more input enable inactive -> every output inactive, whatever the code
The 2-to-4 Decoder With Enable
An n-to-2n binary decoder activates exactly one output: the one whose number equals the binary value on the code inputs. An enable input switches all outputs off when it is inactive.
| E | A | B | D0 | D1 | D2 | D3 |
|---|---|---|---|---|---|---|
| 0 | X | X | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 |
D0 = E . A' . B' D1 = E . A' . B D2 = E . A . B' D3 = E . A . B
Catalog decoders such as the 74x139 (dual 2-to-4) and 74x138 (3-to-8) have active-low outputs and enables, because NAND gates are faster than AND gates in CMOS. The selected output goes LOW and all others stay HIGH. The logic is the same with every output inverted.
Where Are Decoders Used?
Address decoding is the classic use. In a system with four 1 KB memory chips, a 2-to-4 decoder takes address bits A11 and A10 and enables exactly one chip at a time, so address 0x0800 (A11 A10 = 10) selects chip 2. Register files, SRAM row selection and peripheral chip selects work the same way.
Building Bigger Decoders From Smaller Ones
The enable input makes decoders expandable. A 3-to-8 decoder is two 2-to-4 decoders: the top code bit A drives the two enables, and the lower bits B and C go to both decoders.
When A = 0, decoder 0 is enabled and one of D0 to D3 goes active. When A = 1, decoder 1 is enabled and one of D4 to D7 goes active. A 4-to-16 decoder takes five 2-to-4 decoders: one drives the enables of four others.
Quick Check
Q: A 3-to-8 decoder with an active-high enable has the enable at 0 and the code 101. Which outputs are active?
Show Answer
None. With the enable inactive, every output is inactive whatever the code. Only with the enable at 1 would D5 go active.
A Decoder Generates Minterms
Output Dk of an n-input decoder is 1 only for code k, so it is exactly the minterm mk. A decoder plus an OR gate on the outputs a function needs therefore implements any Boolean function. A full adder takes two OR gates behind a 3-to-8 decoder:
Inputs A, B, Cin form the code, the decoder outputs are minterms m0 ... m7 Sum = m1 + m2 + m4 + m7 (odd number of ones) Cout = m3 + m5 + m6 + m7 (two or more ones)
This is rarely the smallest circuit, but it is the right way to think about ROMs and FPGA lookup tables: a ROM is a decoder (the address) driving an OR array (the stored bits).
Quick Check
Q: Which decoder outputs must the Sum OR gate collect in the full adder built from a 3-to-8 decoder?
Show Answer
The minterms with an odd number of ones: m1, m2, m4 and m7.
Large Decoders Use Predecoding
A 6-to-64 decoder is not built from 64 six-input gates, which would be slow and large. It becomes two 3-to-8 predecoders followed by 64 two-input AND gates, one per output. Memory row decoders are built this way.
Where Are Predecoded Decoders Used?
Every SRAM and register-file row decoder splits the address into groups, decodes each group with a small decoder, and combines them with one AND gate per row. This keeps the gate fan-in low and the word-line delay short in arrays with thousands of rows.
Common Mistakes
Mistake #1: Ignoring output polarity
Wrong: Driving active-high chip-select logic from the outputs of an active-low decoder
Right: Check whether the selected output is 1 or 0, and invert or choose the matching device input.
Why? An active-low decoder puts a 0 on the selected output, so the wrong polarity enables every device except the one you wanted.
Mistake #2: Expecting all outputs to be 0 for some code
Wrong: Assuming that code 00 selects nothing
Right: Use the enable input to switch every output off.
Why? An enabled decoder always asserts exactly one output, for every code including 00.
Mistake #3: Using both halves of a bigger decoder without an enable
Wrong: Wiring two 2-to-4 decoders in parallel with the same code and no enable
Right: Drive the enables from the top code bit, as in the 3-to-8 construction.
Why? Without the enable, both decoders are active at once and two outputs (for example D1 and D5) assert for one code.
Practice Exercise
Challenge: Build a 4-to-16 Decoder From 2-to-4 Decoders
You have 2-to-4 decoders with enable. The inputs are D C B A, with D the most significant bit.
- How many 2-to-4 decoders do you need, and how are they connected?
- Which output goes active for D C B A = 1010, and which decoder produces it?
- How many gates does the whole decoder contain if each 2-to-4 decoder is built as in the schematic above?
Hint
Use one decoder on the top two bits to produce four enables, then four decoders on the bottom two bits.
Solution
1. Five decoders. The first takes D and C and is always enabled. Its four outputs drive the enable inputs of four second-level decoders, which all take B and A on their code inputs. Decoder k is enabled when D C = k and produces outputs 4k to 4k+3. 2. D C B A = 1010 is 10 = 4 x 2 + 2, so output 10 goes active. It comes from second-level decoder 2 (D C = 10), where B A = 10 selects output 2. 3. First-level decoder: 2 inverters + 4 two-input ANDs. Each second-level decoder: 2 inverters + 4 three-input ANDs. Total: 10 inverters, 4 two-input ANDs, 16 three-input ANDs = 30 gates.
Summary
In this tutorial, you learned:
- A binary decoder activates exactly one of 2n outputs for each n-bit code, and every output is a minterm
- Enable inputs switch the outputs off and allow a 3-to-8 decoder to be built from two 2-to-4 decoders
- A decoder plus OR gates implements any Boolean function, the idea behind ROMs and lookup tables
- Large decoders are built in predecoded stages: small decoders on groups of address bits, then one AND gate per output
