A sequential circuit is combinational logic plus memory. Its outputs depend on the present inputs and on a stored state that records what happened before. A clock decides when the state is allowed to change. Registers, counters, shift registers and state machines are all sequential, and nearly every digital chip is built as combinational logic between banks of flip-flops.
13 min read | Beginner Level
What You'll Learn
- How memory and feedback make a circuit sequential
- The structure of a synchronous sequential circuit: next-state logic, state registers and output logic
- How to read a state table and trace a circuit clock by clock
- What a register is and how it differs from a latch
Quick Answer: Latch vs. Flip-Flop vs. Register
| Element | Stores | Changes when | Typical use |
|---|---|---|---|
| Latch | 1 bit | The enable level is active (level-sensitive) | Small control circuits, building block of flip-flops |
| Flip-flop | 1 bit | On one clock edge only (edge-triggered) | State bits, pipeline registers |
| Register | n bits | On the clock edge, all bits together | Data words, counters, program counter |
Memory Makes Circuits Sequential
A combinational output is a function of the inputs alone. To remember, a circuit must feed an output back so that it holds its own value. The smallest example is two cross-coupled gates, a latch (see SR Latch Circuit). Edge-triggered flip-flops are built from latches (see D Flip-Flop).
The stored bits are the circuit's state. At each clock edge the flip-flops load a new state computed by the combinational logic from the present state and the inputs.
Structure of a Synchronous Sequential Circuit
This one structure describes every state machine (see Finite State Machines). The flip-flops hold the state, and only the clock edge changes it.
Where Is This Structure Used?
A processor control unit, a bus protocol handler and a traffic-light controller all follow it: some flip-flops hold the current state, and combinational logic decides the next state and the control outputs from the state and the inputs.
Reading a State Table
A state table lists the next state for every combination of present state and inputs. Example: a 2-bit counter with an enable input EN. It counts up by one on each clock edge when EN = 1 and holds its value when EN = 0.
| Present state Q1 Q0 | EN | Next state |
|---|---|---|
| 00 | 0 | 00 |
| 00 | 1 | 01 |
| 01 | 0 | 01 |
| 01 | 1 | 10 |
| 10 | 0 | 10 |
| 10 | 1 | 11 |
| 11 | 0 | 11 |
| 11 | 1 | 00 |
Tracing the circuit means applying the table once per clock edge. Start at 00 with EN = 1, 1, 1, 0, 1, 1:
| Clock edge | EN | State before | State after |
|---|---|---|---|
| 1 | 1 | 00 | 01 |
| 2 | 1 | 01 | 10 |
| 3 | 1 | 10 | 11 |
| 4 | 0 | 11 | 11 |
| 5 | 1 | 11 | 00 |
| 6 | 1 | 00 | 01 |
After six edges the state is 01: the counter reached 11 on edge 3, held on edge 4, then wrapped to 00 and counted to 01.
Quick Check
Q: A 2-bit counter is in state 11 with EN = 1. What is its state after the next clock edge?
Show Answer
00. The counter wraps: 11 + 1 = 100 does not fit in 2 bits, so only the lower two bits, 00, remain.
The 2-bit counter is two D flip-flops with an incrementer, the enable and the reset as combinational logic in front of their D inputs. Only the flip-flops store state; everything in front of them is ordinary combinational logic.
Where Are Registers Used?
Every datapath stage ends in a register: pipeline registers hold intermediate results between stages, configuration registers hold control settings, and counters generate addresses and timeouts.
Common Mistakes
Mistake #1: Confusing a latch with a flip-flop
Wrong: Expecting a latch to sample its input only on an edge
Right: A latch is transparent while its enable is active; a flip-flop samples only at the clock edge.
Why? While a latch is transparent, its output follows the input, so input changes pass straight through. A flip-flop ignores its input between edges.
Mistake #2: Leaving the state undefined at power-up
Wrong: A counter with no reset input
Right: Add a reset that loads a known state.
Why? Flip-flops power up in an unknown state. In simulation the state starts as an unknown value and stays unknown, and in silicon the starting value is random.
Mistake #3: Expecting outputs to change when the input changes
Wrong: Raising EN and expecting the counter to count immediately
Right: The state changes only at the next active clock edge.
Why? Inputs are sampled at the clock edge. Between edges the state is held, which is what makes the circuit predictable.
Practice Exercise
Challenge: Trace a Toggle Circuit
A D flip-flop has its D input connected to its own inverted output (D = Q'). The flip-flop starts at Q = 0.
- Write the state sequence for six clock edges.
- How does the frequency of Q compare with the clock frequency?
- Is the circuit combinational or sequential, and why?
Hint
At each edge, Q takes the value that D had just before the edge.
Solution
1. Edge: 1 2 3 4 5 6 Q: 1 0 1 0 1 0 (starting from Q = 0) 2. Q completes one full cycle (0 -> 1 -> 0) every two clock cycles, so its frequency is half the clock frequency: a divide-by-2 circuit. 3. Sequential: the output depends on the stored state, not only on the inputs (there are no inputs besides the clock at all).
Summary
In this tutorial, you learned:
- A sequential circuit adds memory to combinational logic, so outputs depend on inputs and stored state
- A synchronous circuit has next-state logic, state flip-flops loaded on the clock edge, and output logic
- A state table gives the next state for every present state and input; tracing means applying it once per clock edge
- Give every state bit a reset so the circuit starts from a known state
