Hazards & Glitches

A hazard is a momentary wrong value - a glitch - on the output of combinational logic when its inputs change. It happens because different paths through the logic have different delays, so for a short time the gates see a mix of old and new values. In a clean synchronous design, registers sample only after the logic settles, so glitches do not cause functional errors. They still matter for clocks, asynchronous resets, signals crossing clock domains, and power, because every glitch is a wasted pair of transitions.

13 min read | Intermediate Level

What You'll Learn

• What static and dynamic hazards are, and why unequal path delays cause them
• How to find a static-1 hazard on a K-map and remove it with a consensus term
• Why design tools remove that fix, and when hazards actually matter in synchronous design
• How glitches waste dynamic power, and how designers reduce them

Types of Hazards

Anatomy of a Static-1 Hazard

The classic example is a 2:1 multiplexer written as SOP: y = a·b + a'·c, where a is the select. With b = c = 1, the output should be 1 regardless of a. But when a falls, the term a·b turns off quickly, while a'·c must wait for the inverter to produce a'. For a moment, neither term is 1.

The multiplexer with gate delays (for analysing the glitch)

  inverter   a_n     = NOT a               2 ns   (the slow path)
  AND gate   t1      = a . b               1 ns
  AND gate   t2      = a_n . c             1 ns
  OR gate    y       = t1 + t2             1 ns   (hazard: t1 falls before t2 rises)
  AND gate   t3      = b . c               1 ns   (consensus term)
  OR gate    y_fixed = t1 + t2 + t3        1 ns   (t3 holds the output at 1)

With b = c = 1 and a falling at 10 ns, the expected waveforms are:

A simulation with ideal, zero-delay gates never shows this glitch: every output updates in the same time step. Hazards appear only when gate delays are modelled, as above, or in gate-level simulation with the timing of the real netlist.

Finding and Removing Hazards on a K-Map

A static-1 hazard exists wherever two adjacent 1-cells of the K-map are covered by different product terms, and no single product term covers both. Changing the one variable that differs between those cells hands the output from one term to the other, and the hand-over can leave a gap.

Here the two 1-cells at bc = 11 are adjacent: only a differs between them. But a'c covers one and ab covers the other, so when a changes, the output is handed from one term to the other and can glitch. The fix is to add the product that covers both cells, b·c, called the consensus term:

Hazard-free version

  y = a&b + a'&c + b&c        -- same truth table, no static-1 hazard

The added term is logically redundant: it never changes the truth table. In a two-level SOP circuit, covering every pair of adjacent 1-cells with a shared term removes all static-1 hazards for single-input changes, and such a circuit also has no static-0 or dynamic hazards for single-input changes. Static-0 hazards in POS logic are removed the same way, using sum terms that cover adjacent 0-cells.

Why Hazard Fixes Rarely Survive

Because the consensus term is logically redundant, logic synthesis tools remove it. Optimization minimizes the function; it has no reason to keep a term that does not change the truth table. Mapping onto library cells also reshapes the logic into cells whose internal delays the designer does not control. Hazard-free combinational logic therefore cannot be relied on in a chip built with automatic tools.

The standard answer is not to fight synthesis, but to make sure glitches can never reach anything that is sensitive to them:

Where glitches are harmless vs. dangerous

  HARMLESS: combinational logic between flip-flops of the same clock
            -> the capturing flip-flop samples after the logic settles
               (static timing analysis guarantees this)

  DANGEROUS: anything that reacts to every edge, not just the clock edge
            -> clock pins            (a glitch is an extra clock edge)
            -> asynchronous resets   (a glitch resets the register)
            -> latch enables         (a glitch opens the latch)
            -> signals entering a synchronizer from another clock domain
            -> chip outputs driving asynchronous external devices

  RULE: drive these from a flip-flop output, never from combinational logic

Risky : a decoded signal used as an asynchronous clear
          clear = NOT (state is the ERROR code)    -> combinational, may glitch
          a glitch on clear resets the register

Safe  : register the decoded value first, then use the flip-flop output
          clear_q <= NOT (state is the ERROR code)  at each clock edge
          -> changes only on a clock edge, so it cannot glitch

Glitches and Power

Even when glitches are functionally harmless, each one is a pair of extra transitions that charges and discharges capacitance. That is dynamic power spent for nothing.

Glitch power in proportions

  more paths with unequal delays converging on a gate  ->  more glitches
  deeper logic (more levels)                           ->  glitches multiply along the path
  each glitch = one extra 0->1->0 (or 1->0->1)         ->  energy of a full transition

  worst offenders: array multipliers, adders, XOR-heavy datapaths

Common Mistakes

Mistake #1: Adding consensus terms and expecting them to survive the tools

Logic synthesis removes logically redundant terms. A hazard fix written into the logic equations disappears from the netlist. If a glitch-free signal is needed, generate it from a flip-flop instead of relying on combinational structure.

Mistake #2: Trusting zero-delay simulation to reveal hazards

A functional simulation has no gate delays, so it never shows glitches. Hazards appear only when delays are modelled or in gate-level simulation with real timing, which is why glitch-related bugs are often found late.

Mistake #3: Driving clocks or asynchronous resets from combinational logic

A clock or asynchronous reset reacts to every edge, including a glitch. Decoded clocks, clock muxes built from plain gates, and resets derived from state decodes are classic sources of intermittent failures. Use a register or a dedicated clock-gating or clock-mux cell.

Mistake #4: Assuming glitches never matter in synchronous logic

Glitches are functionally harmless between flip-flops of the same clock, but they still consume power, and they become dangerous at clock-domain crossings and asynchronous interfaces. "Synchronous" is not a blanket guarantee.

Practice Exercise

Challenge: Find and Fix the Hazard

f(A, B, C) = A'B' + BC.

1. Draw the K-map and identify the static-1 hazard: which variable changes, and with what values of the other two?
2. Give the consensus term that removes it.
3. This signal drives an asynchronous reset. Is adding the consensus term to the logic a good fix? What would you do instead?

Hint

Look for two adjacent 1-cells covered by A'B' and BC but not by a common term. B is the variable that appears true in one term and complemented in the other.

Solution

1. Cells 001 and 011 are adjacent (only B changes, with A = 0, C = 1).
   001 is covered only by A'B'; 011 only by BC -> static-1 hazard
   when B changes while A = 0 and C = 1.

2. Consensus term: A'C   ->  f = A'B' + BC + A'C

3. No. The synthesis tool removes A'C as redundant, and even if kept, other
   delay effects can still glitch. Register the signal and drive the
   asynchronous reset from the flip-flop output (or use a proper
   reset synchronizer).
  

Summary

In this tutorial, you learned:

• Hazards are brief wrong output values caused by unequal delays along different logic paths
• Static-1 and static-0 hazards glitch an output that should stay constant; dynamic hazards add extra transitions to a changing output
• On a K-map, adjacent 1-cells covered by different terms indicate a static-1 hazard; a consensus term removes it
• Logic synthesis removes consensus terms because they are logically redundant
• Between flip-flops of one clock, glitches are harmless; on clocks, asynchronous resets, latch enables, and CDC paths they cause failures
• Glitches waste dynamic power, especially in deep arithmetic logic
• A zero-delay functional simulation cannot show hazards; gate-level simulation with timing can