A CMOS NAND gate puts its NMOS transistors in series and its PMOS transistors in parallel. The output is pulled LOW only when every series NMOS is ON - that is, when all inputs are HIGH - and any single input going LOW turns on a PMOS that pulls the output HIGH. This structure makes NAND the fastest and most area-efficient multi-input gate in CMOS, which is why standard-cell libraries lean so heavily on it.
13 min read | Intermediate Level
What You'll Learn
- How series NMOS and parallel PMOS implement the NAND function
- How to size a NAND gate so it drives as strongly as an inverter
- Why NAND is preferred over NOR in CMOS
- Why a non-inverting gate costs an extra stage, and how NAND cells appear in standard-cell netlists
The NAND2 Circuit
Read the circuit one network at a time:
- Pull-down (series NMOS): current can flow from Y to GND only through NA and NB. Both must be ON, so Y is pulled LOW only when A = 1 and B = 1.
- Pull-up (parallel PMOS): either PA or PB can connect Y to VDD. If A = 0 or B = 0, at least one PMOS is ON and Y is HIGH.
| A | B | PA | PB | NA | NB | Y |
|---|---|---|---|---|---|---|
| 0 | 0 | ON | ON | OFF | OFF | 1 |
| 0 | 1 | ON | OFF | OFF | ON | 1 |
| 1 | 0 | OFF | ON | ON | OFF | 1 |
| 1 | 1 | OFF | OFF | ON | ON | 0 |
In every row, exactly one network conducts. The two networks are duals: series in one becomes parallel in the other. Series transistors implement AND of their conditions; parallel transistors implement OR.
Reading any static CMOS gate pull-down network conducts -> output = 0 series NMOS -> AND of the inputs parallel NMOS -> OR of the inputs output = NOT (pull-down condition) NAND2: pull-down = A AND B -> Y = NOT (A AND B)
The Internal Node
Between the two series NMOS there is a node that exists only inside the gate, call it n1: NA connects Y to n1, and NB connects n1 to ground. When B is 0, NB is OFF, so n1 is cut off from ground and the pull-down path is open, whatever A is. That is exactly why a single input at 0 is enough to stop the output from being pulled low. The capacitance of n1 also has to be charged and discharged, which is one reason a stack of series transistors is slower than a single transistor.
What Maps to What
| Function | Cell | Transistors |
|---|---|---|
| Y = NOT(A·B) | One NAND2 cell | 4 |
| Y = A·B | AND2 cell: internally a NAND2 followed by an inverter | 6 |
| Y = NOT(A·B·C) | One NAND3 cell: 3 series NMOS, 3 parallel PMOS | 6 |
Notice that a plain AND costs more than a NAND. In static CMOS every single-stage gate is inverting, so a non-inverting function needs an extra inverter stage. Synthesis tools exploit this: they restructure logic so that inversions cancel across stages, and the resulting netlists are dominated by NAND, NOR, and AND-OR-INVERT cells rather than AND and OR.
Quick Check
Q: Y = NOT(A·B)·C. What is the cheapest way to build this, and why does an AND2 cell not come out directly?
Show Answer
A NAND2 for NOT(A·B), then an AND with C. An AND is itself NAND + inverter, so a tool may instead restructure the whole expression, for example as NOT(NOT(NOT(A·B)·C)) using NAND2 cells and one inverter, or pick a single complex cell if the library has one. Single CMOS stages are always inverting, so non-inverting functions cost an extra stage.
Sizing: Making NAND2 as Strong as an Inverter
Series transistors add their resistances. Two NMOS in series, each the same width as an inverter's NMOS, have about twice the resistance, so the NAND2 pulls down only half as fast. To compensate, each series transistor is made about twice as wide.
Sizing a NAND2 to match a reference inverter (NMOS width 1, PMOS width 2)
pull-down: 2 NMOS in series
each needs half the resistance -> width 2 each
worst case (both ON in series): same strength as inverter NMOS
pull-up: 2 PMOS in parallel
worst case = only ONE is ON (one input low)
that one must match the inverter PMOS -> width 2 each
input capacitance per input = NMOS 2 + PMOS 2 = 4
inverter input capacitance = NMOS 1 + PMOS 2 = 3
-> each NAND2 input loads its driver 4/3 as much as an inverter
That ratio, 4/3, is the NAND2's logical effort: how much more input capacitance it presents than an inverter with the same output drive. Lower is better, because it means less work for the gate driving it.
Why NAND Beats NOR in CMOS
NAND stacks its fast transistors (NMOS, electrons) in series and puts the slow ones (PMOS, holes) in parallel. NOR does the opposite, stacking the slow PMOS in series. Widening a series stack to compensate is cheaper when the transistors are already small and fast.
| Gate (2 inputs) | Series stack | Transistor widths (NMOS / PMOS) | Input capacitance | Logical effort |
|---|---|---|---|---|
| Inverter | none | 1 / 2 | 3 | 1 |
| NAND2 | NMOS | 2 / 2 | 4 | 4/3 ≈ 1.33 |
| NOR2 | PMOS | 1 / 4 | 5 | 5/3 ≈ 1.67 |
The gap widens with more inputs: a NAND4 has a logical effort of 2, while a NOR4 has 3. Series stacks also add internal capacitance and body effect, so practical libraries rarely go beyond four transistors in series.
Where Does NAND Dominate?
Synthesized netlists for processors, GPUs, and network chips typically contain far more NAND and AOI cells than NOR or OAI cells, because they give the best speed per unit area. Flash memory takes the idea further: NAND flash strings dozens of memory transistors in series, trading read speed for extremely dense storage, which is how it earned its name.
Where Do Universal Gates Show Up?
Because any logic function can be built from NAND gates alone, NAND2 cells are often used as the unit of area. Synthesis and IP datasheets commonly quote design size in "gate equivalents" - the area of one NAND2 cell - so a block described as 500K gates occupies roughly the area of 500,000 NAND2 cells.
Common Mistakes
Mistake #1: Sizing series transistors the same as an inverter's
Two NMOS in series have about twice the resistance of one. If each is inverter-sized, the NAND2's falling edge is roughly twice as slow. Series transistors must be widened in proportion to the stack height to match inverter drive.
Mistake #2: Sizing parallel transistors for the best case
With both PMOS ON, a NAND2 pulls up strongly, but timing must hold when only one input is LOW and only one PMOS conducts. Each parallel transistor must be strong enough on its own.
Mistake #3: Expecting AND to be cheaper than NAND
In CMOS an AND2 is a NAND2 plus an inverter: more transistors and one extra stage of delay. Writing logic in terms of AND/OR is fine, because synthesis restructures it, but when reasoning about gate counts and delay, remember that inverting gates are the natural building blocks.
Mistake #4: Building very wide NAND gates in one stage
A NAND8 would need 8 NMOS in series, each very wide, with a large internal capacitance and a slow pull-down. Wide functions are faster as a tree of smaller gates, for example two NAND4s combined by a NOR2. Synthesis does this automatically; it matters when you hand-design or read netlists.
Practice Exercise
Challenge: Size and Model a NAND3
- Using a reference inverter with NMOS width 1 and PMOS width 2, size a NAND3 so its worst-case drive matches the inverter. What is its input capacitance per input, and its logical effort?
- Describe the pull-up and pull-down networks of the NAND3, including the internal nodes of the series stack.
Hint
Three NMOS in series each need one third of the resistance. The parallel PMOS must each match the inverter PMOS on their own.
Solution
1. NMOS: 3 in series -> width 3 each
PMOS: 3 in parallel -> width 2 each (worst case one ON)
Input capacitance per input = 3 + 2 = 5
Logical effort = 5 / 3 = ~1.67
2. Pull-up: PA, PB and PC in parallel, each between VDD and Y.
Pull-down: NA, NB and NC in series: Y -> n1 -> n2 -> GND,
so the stack has two internal nodes, n1 and n2.
Summary
In this tutorial, you learned:
- A CMOS NAND has series NMOS in the pull-down and parallel PMOS in the pull-up
- Series transistors implement AND of their conditions; parallel transistors implement OR
- The pull-up and pull-down networks are duals, so exactly one conducts for every input combination
- Series transistors must be widened to match inverter drive, giving NAND2 a logical effort of 4/3
- NAND is preferred over NOR because it stacks the faster NMOS in series
- Every single CMOS stage is inverting, so AND costs a NAND plus an inverter
