CMOS power has three parts. Dynamic power is spent charging and discharging capacitance every time a node toggles, and it grows with the square of the supply voltage. Short-circuit power flows briefly while both transistor networks are partly ON during a transition. Static (leakage) power flows all the time through transistors that are supposed to be OFF. Every low-power technique targets one or more of these three.
14 min read | Intermediate Level
What You'll Learn
- Where dynamic power comes from, and how activity, capacitance, voltage, and frequency set it
- When short-circuit power matters and how to keep it small
- Why leakage has become a major share of power in advanced processes
- How design choices such as clock gating cut activity, and what hardware implements them
The Three Components at a Glance
| Component | When it flows | Grows with | Main countermeasures |
|---|---|---|---|
| Dynamic (switching) | Every time a node toggles | Activity, capacitance, VDD2, frequency | Clock gating, lower VDD, less switched capacitance |
| Short-circuit | During input transitions, while both networks conduct | Slow input edges, VDD | Sharp, matched edge rates |
| Static (leakage) | Always, while powered | Low Vth, temperature, number of transistors | High-Vt cells, power gating, lower temperature |
Dynamic Power: Charging Capacitance
Every gate output drives a capacitance C_L. When the output rises, the PMOS charges C_L from the supply; when it falls, the NMOS discharges it to ground.
Charging C_L to VDD draws an energy of C_L × VDD2 from the supply. Half of it is stored on the capacitor; the other half is lost as heat in the PMOS. On the falling edge, the stored half is dumped to ground as heat in the NMOS. So every full 0 → 1 → 0 cycle turns C_L × VDD2 of energy into heat, no matter how strong or weak the transistors are.
Dynamic power in proportions
dynamic power proportional to activity x capacitance x VDD^2 x frequency
activity (alpha) : fraction of clock cycles in which a node makes a 0->1 transition
capacitance : total switched capacitance (gate inputs + wires + diffusion)
VDD^2 : energy per transition grows with the SQUARE of voltage
frequency : transitions per second
VDD -10% -> dynamic power ~ -19% (0.9^2 = 0.81)
VDD -30% -> dynamic power ~ -51% (0.7^2 = 0.49)
freq /2 -> dynamic power /2
activity /2 -> dynamic power /2
Voltage is the strongest lever, because it enters squared. And since lower voltage also forces a lower maximum clock frequency, scaling voltage and frequency together reduces dynamic power roughly with the cube of the voltage reduction.
Quick Check
Q: A block has 2 nF of switched capacitance, an average activity factor of 0.1, VDD = 0.8 V, and runs at 1.5 GHz. Estimate its dynamic power.
Show Answer
0.1 × 2 nF × (0.8 V)2 × 1.5 GHz = 0.1 × 2e-9 × 0.64 × 1.5e9 = 0.192 W, or about 190 mW.
Where Is Voltage Scaling Used?
Phone and laptop processors use dynamic voltage and frequency scaling (DVFS): they run at high voltage and frequency for bursts of demanding work, then drop both whenever the load is light. Because dynamic power falls with the square of voltage, running a light task at a lower voltage and frequency uses far less energy than racing through it at full speed in many situations.
Short-Circuit Power: Both Networks Briefly ON
During an input transition, there is a window where the input is above the NMOS threshold but below VDD minus the PMOS threshold. In that window both networks conduct, and current flows straight from VDD to GND without charging anything useful.
Short-circuit power proportion rules slower input edge -> longer window with both networks ON -> more short-circuit energy faster output edge relative to input -> bigger overlap current matched input/output transition times -> short-circuit power typically < 10% of dynamic lower VDD (closer to Vtn + |Vtp|) -> window shrinks, short-circuit power drops sharply
This is one reason timing tools enforce a maximum transition time on every net. Slow edges waste power and are more sensitive to noise, so nets with slow edges get stronger drivers or buffers.
Static Power: Leakage
An OFF transistor still conducts a small leakage current, mostly subthreshold current, plus gate tunnelling and junction leakage. Each transistor leaks very little, but a chip has billions of them, and every one leaks as long as its block is powered.
Leakage proportion rules lower Vth -> exponentially more leakage (about 10x per 70-100 mV) higher temperature -> more leakage more transistors -> more leakage (proportional) clock stopped -> leakage UNCHANGED (still powered) supply switched off -> leakage removed (except for the power switches)
The Voltage Trade-Off
Lowering VDD is the best tool for dynamic power, but it pushes the supply closer to the transistor threshold voltage. That shrinks the overdrive and slows every gate. The obvious fix, lowering Vth, multiplies leakage.
The central tension
lower VDD -> dynamic power falls as VDD^2 (good)
-> overdrive (VDD - Vth) shrinks -> slower (bad)
restore speed by lowering Vth
-> leakage rises exponentially (bad)
Result: designs use several voltage domains and several Vt flavours,
matching each block's voltage and Vth to its speed needs.
Where Is This Trade-Off Managed?
Modern SoCs split the chip into multiple voltage domains: always-on control logic at a low fixed voltage, CPU clusters on scalable supplies, and memories on their own rails. A power intent file (UPF) describes the domains, level shifters between them, and which domains can be switched off. Implementation and verification tools use it to insert and check the power-management cells.
What the Designer Controls: Activity and Clock Gating
The logic design cannot change VDD or Vth, but it largely decides activity. The biggest single source of activity is the clock network, which toggles every cycle and drives every flip-flop. Stopping the clock to registers that are not changing saves their clock power and the clock-tree power feeding them.
A 32-bit register that loads only when enabled (EN)
Without clock gating (enable mux):
D ---[mux: EN ? D : Q]---> [FF] ---> Q one mux per flip-flop
the clock still toggles all 32 flip-flops every cycle; when EN = 0
each flip-flop reloads its own value
With clock gating:
CLK ---[ICG cell, enabled by EN]---> gated clock ---> 32 flip-flops
when EN = 0 the gated clock stops, so no flip-flop clock pin toggles
How it is built: without clock gating, each flip-flop gets a feedback multiplexer that reloads its own value when EN is 0. With clock gating, one integrated clock-gating (ICG) cell stops the clock to all 32 flip-flops when EN is 0. The feedback muxes disappear, and the clock pins stop toggling. Synthesis tools can insert ICG cells automatically when they see a shared enable.
| Implementation | Clock toggles at flip-flops when en = 0? | Extra logic |
|---|---|---|
| Enable mux (no clock gating) | Yes, every cycle | 32 two-input muxes |
| Clock gating (ICG cell) | No | 1 ICG cell (a latch plus an AND gate) |
Other design habits also cut activity: avoiding needless toggling on wide buses when data is not valid, and not resetting or updating large registers every cycle when they do not need to change.
Where Does Clock Gating Pay Off?
In typical processors and SoCs, the clock network and flip-flops account for a large share of dynamic power, often cited as a third or more. Automatic clock gating in synthesis is enabled on nearly every modern design, and power reports list the percentage of registers that are gated as a standard quality metric.
Common Mistakes
Mistake #1: Forgetting that dynamic power scales with VDD squared
A 10% supply reduction saves about 19% of dynamic power, not 10%. Treating voltage as a linear knob badly underestimates its value, and misjudges the cost of running blocks at a higher voltage than they need.
Mistake #2: Expecting clock gating to reduce leakage
Clock gating stops switching, so it removes dynamic power. The gated logic is still powered and still leaks. Only power gating or higher-Vt cells reduce leakage.
Mistake #3: Gating a clock with an ordinary AND gate
Combining the clock with the enable in a plain AND gate (gated clock = CLK AND EN) can produce glitches on the gated clock when EN changes while CLK is HIGH, causing false clock edges. Use a proper latch-based ICG cell, which holds EN steady while the clock is high.
Mistake #4: Oversizing cells that do not need the speed
Energy per transition is C × VDD2, independent of how fast the edge is. Oversized cells increase C (their own diffusion and input capacitance), so they raise switching energy even when their extra speed is not needed.
Practice Exercise
Challenge: Budget a Block's Power
A block has 4 nF of switched capacitance with an average activity of 0.15. It runs at 1 GHz and 0.9 V, and leaks 30 mW.
- Estimate its dynamic power and total power (ignore short-circuit power).
- DVFS drops it to 0.7 V and 600 MHz for a light workload. Estimate the new dynamic power. Assume leakage falls to 20 mW at the lower voltage.
- Clock gating reduces the average activity by one third. What is the dynamic power at the original operating point?
Hint
Use activity x capacitance x VDD2 x frequency. Scale each factor separately for parts 2 and 3.
Solution
1. Dynamic = 0.15 x 4e-9 x 0.9^2 x 1e9 = 0.486 W
Total = 0.486 + 0.030 = ~0.52 W
2. Dynamic = 0.15 x 4e-9 x 0.7^2 x 0.6e9 = 0.176 W
Total = 0.176 + 0.020 = ~0.20 W
(voltage alone cut the energy per transition to 0.49/0.81 = 60% of its
original value, and the lower frequency cut the power by a further 40%)
3. Activity 0.15 -> 0.10:
Dynamic = 0.10 x 4e-9 x 0.81 x 1e9 = 0.324 W (one third lower)
Summary
In this tutorial, you learned:
- CMOS power has dynamic, short-circuit, and static (leakage) components
- Dynamic power is proportional to activity x capacitance x VDD2 x frequency
- Every full charge-discharge cycle of a node turns C x VDD2 of energy into heat
- Short-circuit power is usually under 10% of dynamic power when edges are sharp and matched
- Leakage flows whenever a block is powered and grows as Vth drops and temperature rises
- Lowering VDD saves power but costs speed, and lowering Vth to recover speed costs leakage
- The designer mostly controls activity; a shared register enable lets a clock-gating cell stop the clock to a whole group of flip-flops
