A shift register is a chain of flip-flops that share one clock, with each output feeding the next input, so data moves one position on every clock edge. It converts between serial and parallel data, delays a signal by a fixed number of cycles, and with feedback it generates counting sequences. The serial interfaces of nearly every chip rely on it.
13 min read | Intermediate Level
What You'll Learn
- How serial-in and parallel-in shift registers move data, and how SISO, SIPO, PISO and universal registers differ
- How to trace a shift register clock by clock
- How ring and Johnson counters use feedback around a shift register
Quick Answer: Shift Register Types
| Type | Input | Output | Clocks to load N bits | Typical use |
|---|---|---|---|---|
| SISO | Serial | Serial | N | Delay line |
| SIPO | Serial | Parallel | N | Serial-to-parallel conversion |
| PISO | Parallel | Serial | 1 (parallel load) | Parallel-to-serial conversion |
| PIPO | Parallel | Parallel | 1 | Storage register |
| Universal | Either | Either | 1 or N | Shift left/right, load, hold |
Shift register proportion rules one clock edge -> every bit moves one position N flip-flops -> data appears at the output N clocks after it enters N-bit serial transfer -> N clock cycles
Serial-In, Parallel-Out (SIPO)
The serial input feeds the first flip-flop. On each clock edge every bit moves one flip-flop onward and a new bit enters. After N clocks the first bit has reached the last flip-flop, and all N bits can be read in parallel.
Shifting in the bits 1, 0, 1, 1 (first bit first), with the first flip-flop on the right:
| Clock | Serial in | Q3 | Q2 | Q1 | Q0 |
|---|---|---|---|---|---|
| Initial | - | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 |
| 2 | 0 | 0 | 0 | 1 | 0 |
| 3 | 1 | 0 | 1 | 0 | 1 |
| 4 | 1 | 1 | 0 | 1 | 1 |
After four clocks Q3 Q2 Q1 Q0 = 1011: the first bit sent ended up in Q3, the most significant position.
Quick Check
Q: A 4-bit SIPO register is cleared and receives the serial bits 0, 1, 1, 0 (first bit first). What are Q3 Q2 Q1 Q0 after four clocks?
Show Answer
The first bit shifts all the way to Q3: Q3 Q2 Q1 Q0 = 0110.
Where Are SIPO Registers Used?
Serial receivers collect incoming bits into a byte before the processor reads it. Output expanders turn three microcontroller pins (data, clock, latch) into eight or more parallel outputs for LEDs and displays.
Parallel-In, Serial-Out (PISO)
A PISO register has a multiplexer in front of every flip-flop: when LOAD is active the flip-flops capture the parallel word, and otherwise they shift. The serial output is the last flip-flop.
Load 1011 and shift left (the most significant bit leaves first), shifting in 0:
| Step | Mode | Q3 | Q2 | Q1 | Q0 | Serial out (Q3) |
|---|---|---|---|---|---|---|
| Load | - | 1 | 0 | 1 | 1 | 1 |
| 1 | shift | 0 | 1 | 1 | 0 | 0 |
| 2 | shift | 1 | 1 | 0 | 0 | 1 |
| 3 | shift | 1 | 0 | 0 | 0 | 1 |
| 4 | shift | 0 | 0 | 0 | 0 | 0 |
The serial output shows 1, 0, 1, 1 in successive steps: the original word, most significant bit first.
Where Are PISO Registers Used?
Serial transmitters load a byte in parallel and clock it out one bit at a time. Input expanders sample many switches at once and send them to a microcontroller over a short serial link.
Universal Shift Register
A universal shift register adds a mode select, so one block can hold, shift right, shift left or load in parallel:
| S1 | S0 | Operation |
|---|---|---|
| 0 | 0 | Hold |
| 0 | 1 | Shift right |
| 1 | 0 | Shift left |
| 1 | 1 | Parallel load |
Each flip-flop has a 4-to-1 multiplexer on its D input choosing between its own output, a neighbour on either side, or the parallel input.
Rings and Twisted Rings: Counting With a Shift Register
Feeding the output back to the input turns a shift register into a counter. A ring counter circulates a single 1, giving one-hot states. A Johnson (twisted-ring) counter feeds back the inverted output and has twice as many states for the same flip-flops.
| Clock | Ring counter (4 FF) | Johnson counter (4 FF) |
|---|---|---|
| 0 | 1000 | 0000 |
| 1 | 0100 | 1000 |
| 2 | 0010 | 1100 |
| 3 | 0001 | 1110 |
| 4 | - | 1111 |
| 5 | - | 0111 |
| 6 | - | 0011 |
| 7 | - | 0001 |
| Ring counter | Johnson counter | |
|---|---|---|
| States with N flip-flops | N | 2N |
| Decoding a state | One flip-flop output | Two adjacent outputs |
| Self-starting | No (needs initialization to one-hot) | No (needs initialization) |
Where Are Ring and Johnson Counters Used?
Sequencers that need clean, glitch-free timing phases use them because each phase is a one-hot output (ring) or needs only a two-input gate to decode (Johnson), and a Johnson counter changes only one bit per step, so its decoded phases are free of glitches.
Quick Check
Q: A 4-bit Johnson counter is in state 1110. What is the next state, and how many distinct states does it cycle through?
Show Answer
The next state is 1111. A Johnson counter with 4 flip-flops cycles through 8 states (2N).
Implementation Notes
An N-bit shift register is N D flip-flops connected in a chain, with a multiplexer in front of each flip-flop if there is a load or direction control. In an FPGA, a long SISO shift register is often mapped to shift-register LUTs or a memory block instead of individual flip-flops.
Common Mistakes
Mistake #1: Expecting data to pass through all stages in one clock
Wrong: Assuming a bit reaches the output of a 4-stage register at the next clock edge
Right: Data moves one stage per clock edge: N stages need N edges.
Why? All flip-flops sample at the same edge, and each sees the old output of the stage before it.
Mistake #2: Reading a SIPO register before it is full
Wrong: Using the parallel output after fewer than N clocks
Right: Wait N clock edges, or qualify the word with a counter or a "word complete" flag.
Why? Until N bits have been shifted in, the register still holds bits from the previous word.
Mistake #3: Mixing up the bit order
Wrong: Shifting left but sending the least significant bit first
Right: Match the shift direction to the bit order of the protocol (MSB first for a left shift).
Why? The first bit shifted in ends up at the far end of the register, so the order of transmission fixes the bit positions of the received word.
Practice Exercise
Challenge: Receive a Byte and Detect a Pattern
A 4-bit SIPO register (first flip-flop on the right, shifting toward Q3) receives the serial stream 1, 1, 0, 1, 1, 0, 1, 1.
- Give Q3 Q2 Q1 Q0 after each of the first four clocks, starting from 0000.
- After the eighth clock, what are Q3 Q2 Q1 Q0?
- A Johnson counter needs exactly 10 states. How many flip-flops does it need?
Hint
Each new bit enters at Q0 and every other bit moves one place to the left.
Solution
1. and 2. clock 1: bit 1 -> Q3 Q2 Q1 Q0 = 0001 clock 2: bit 1 -> Q3 Q2 Q1 Q0 = 0011 clock 3: bit 0 -> Q3 Q2 Q1 Q0 = 0110 clock 4: bit 1 -> Q3 Q2 Q1 Q0 = 1101 clock 8: bit 1 -> Q3 Q2 Q1 Q0 = 1011 The register always holds the last four bits received. 3. A Johnson counter has 2N states, so 10 states need N = 5 flip-flops.
Summary
In this tutorial, you learned:
- A shift register passes data one flip-flop per clock edge; N bits take N clocks to shift in serially
- SISO delays, SIPO converts serial to parallel, PISO converts parallel to serial with a load/shift multiplexer, and a universal register adds modes
- Feedback turns it into a counter: a ring counter has N one-hot states, a Johnson counter has 2N states
- All stages sample at the same edge, so each flip-flop copies the old output of the one before it
